Error correction device

ABSTRACT

In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.

This application is a division of application Ser. No. 09/848,218, filedMay 4, 2001.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to error correction, and morespecifically, to an error correction device used for optical diskshaving a data structure composed of a main data unit and a parity unit.

(2) Description of the Prior Art

In recent years, DVDs (digital versatile discs) and CD-ROMs (compactdisc-read-only memories) for recording digital data at high densitieshave come to be widely used. The digital data, which are recorded orread by a laser, are very small in size. No matter how carefully thesemedia may be fabricated or handled, it is difficult to prevent them fromgetting fingerprints or blemishes on their surface.

Hence, the use of error correcting technology is essential. However, insuch a case where 1-bit parity is merely appended to every 7-bit maindata, if an error arises, its presence is known but its location and theoriginal data remain unknown. Moreover, if two errors arise, theiroccurrence itself is unknown. To solve this problem, as shown in FIGS. 1and 2, error correction is performed by providing data with parityhaving a complicated structure in the vertical and the horizontaldirection. According to this system, even if several errors arise, theywill be found in real time and corrected.

There have been various techniques developed as methods for appendingparity, one of them being RS code correction which comes down errorcorrection to a question of solving a numerical formula. Since RS codecorrection is a known art shown in FUGO RIRON NYUMON or Introduction tothe Theory of Codes written by Iwatare and published by Shoseido, JISSENAYAMARI TEISEI GIJUTU, or A Hands-on Technique of Error Correctionpublished by TRICEPTS, and the like, its description will be omitted.

In optical disks such as DVDs and CD-ROMs, error correction of data isperformed in compliance with individual data formats.

The following is a description of error correction for a DVD. The dataformat in one sector is shown in FIG. 1, and the data format in oneblock including error correcting codes (ECCs) is shown in FIG. 2. Asshown in FIG. 1, one sector includes a header, main data, and an errordetecting code (EDC). The block including the ECCs shown in FIG. 2contains the sector shown in FIG. 1, and has product codes with innercode parity for horizontal error correction and outer code parity forvertical error correction. (In the present specification, as a rule, thesector shown in FIG. 1+the inner code parity on the right side in FIG. 2is referred to as a sector).

In an error correction device for DVDs, it is general that demodulateddata are temporarily written in the buffer memory and read later inorder to execute error correction for the data in the buffer memorybecause error correction in real time takes much time, considering it isdone by an electronic device, and has to be repeated until no error isleft. In this case, there are horizontal error correction with innercode parity and vertical error correction with outer code parity.

In horizontal error correction for consecutive main data such as imagedata, syndrome calculation is performed every code word (string)(consisting of 172-byte data and 10-byte inner code parity) to detect anerror-containing code, and error correction is performed by calculatingthe position and value of the error, based on the data of the detectedcode. In vertical error correction, syndrome calculation is performedevery code word (consisting of 192-byte data and 16-byte outer codeparity) to detect an error-containing code, and the position and valueof the error are calculated, based on the data of the detected code.Following error correction repeated for a predetermined number of timesin the horizontal direction first and then in the vertical direction,error detection is performed in order to check to see that no errorremains in the data (or that the error correction is successfully done)by using each EDC. If no error is detected, this means that the errorcorrection is complete.

Then, data in the buffer memory whose error has been corrected aretransmitted downstream, and data in the next sector obtained fromupstream are written in the buffer memory.

A prior art error correction device is shown in FIG. 3. This devicecomprises a system control unit 1 which controls the entire system, aDMA control unit 2 which controls DMA (direct memory access) transferdescribed below between buffer memory and each unit, a bus control unit3, a buffer memory 4 which stores demodulated data, a syndromecalculator 5 for generating syndrome that is an equation to be solvedfor error correction, an error corrector 6 which performs errorcorrection by calculating the position and value of an error, based onthe syndrome generated by the syndrome calculator 5, and an errordetector 7 which detects the presence or absence of an error in the datawhich has been subjected to error correction, or which checks to seethat all errors have been corrected. The bus control unit 3, the buffermemory 4, the syndrome calculator 5, the error corrector 6, and theerror detector 7 are connected with each other via a data bus 11.

A DMA command 12 is transmitted from the system control unit 1 to theDMA control unit 2 in order to provide instructions to execute DMA. (Thedrawing shows the signal line of the command 12 for the sake ofconvenience. This holds true for the other signals). A DMA request 13 istransmitted from the DMA control unit 2 to the bus control unit 3 inorder to request DMA. A buffer memory access signal 14 is transmitted toexecute the reading or writing of data from or to the buffer memory 4. Asyndrome data supply signal 15 indicates the supply of data in thebuffer memory 4 to the syndrome calculator 5. Syndrome 16 is the productin the syndrome calculator 5.

An access request signal 17 is transmitted from the error corrector 6 tothe bus control unit 3 in order to request access to the buffer memory4. An error corrector access signal 18 is transmitted to execute thereading or writing of data from or to the error corrector 6. An errorcorrection completion signal 19 indicates that error correction iscompleted in the error corrector 6. An error detector data supply signal20 indicates the supply of data from the buffer memory 4 to the errordetector 7. An error detection signal 21 indicates whether or not anerror has been detected by the error detector 7.

FIG. 4 shows the procedure of horizontal error correction in one sector.

The procedure of horizontal error correction in one sector in the priorart error correction device will be described as follows with referenceto FIGS. 3 and 4.

Step (a-1): the system control unit 1 outputs the DMA command 12 to theDMA control unit 2 so as to provide instructions to transfer dataequivalent to one code word×13 times from the buffer memory 4 to thesyndrome calculator 5.

Step (a-2): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the syndrome calculator 5.

Step (a-3): the bus control unit 3 puts the data bus 11 in commission,and outputs the buffer memory access signal 14 and the syndrome datasupply signal 15 to the buffer memory 4 and the syndrome calculator 5,respectively, so as to execute the data transfer from the buffer memory4 to the syndrome calculator 5.

Step (a-4): the syndrome calculator 5 performs error detection everytransferred code word, and outputs the syndrome 16 to the errorcorrector 6 if there is an error.

Step (a-5): the error corrector 6 calculates the position and value ofthe error, based on the syndrome 16. In order to correct an error indata on the buffer memory 4, the error corrector 6 provides the buscontrol unit 3 with the access request signal 17, thereby requestingreadout of the error-containing data.

Step (a-6): after putting the data bus 11 in commission, the bus controlunit 3 outputs the buffer memory access signal 14 and the errorcorrector access signal 18 to the buffer memory 4 and the errorcorrector 6, respectively, reads error-containing data from the buffermemory 4, and supplies the data to the error corrector 6.

Step (a-7): after correcting the error in the data supplied, the errorcorrector 6 transmits the access request signal 17 to the bus controlunit 3 again so as to request writing of the error-corrected data in thebuffer memory 4.

Step (a-8): after putting the data bus 11 in commission, the bus controlunit 3 reads the error-corrected data from the error corrector 6 andoverwrites the data in the buffer memory 4. At the same time, the errorcorrector 6 transmits the correction completion signal 19 to the systemcontrol unit 1.

Step (a-9): in order to check to see that the corrected data contain nomore error, the system control unit 1 transmits the DMA command 12 tothe DMA control unit 2 so as to provide instructions to transfer thedata from the buffer memory 4 to the error detector 7.

Step (a-10): the DMA control unit 2 outputs the DMA request 13 to thebus control unit 3 so as to request the data transfer from the buffermemory 4 to the error corrector 7.

Step (a-11): after putting the data bus 11 in commission, the buscontrol unit 3 outputs the buffer memory access signal 14 and the errordetector data supply signal 20 to the buffer memory 4 and the errordetector 7, respectively, so as to execute the data transfer from thebuffer memory 4 to the error detector 7.

Step (a-12): the error detector 7 performs error detection for the datatransferred, and transmits the error detection signal 21 to the systemcontrol unit 1 in order to inform whether an error has been detected ornot.

Through these steps, the horizontal error correction for one sector iscomplete.

In the same manner, horizontal error correction is executed for thesubsequent 15 sectors including the outer code parity unit so as tocomplete the horizontal error correction for one block. If no error isdetected from all sectors, the error correcting operation is complete;if there is an error detected even from one sector, the next processincluding vertical error correction will be executed.

The above-described prior art method, however, takes much time in aseries of operations: the syndrome calculation by the syndromecalculator 5, the error correction by the error corrector 6, and theerror detection by the error detector 7 done in this order. Above all,it is time-consuming to access the buffer memory 4 as storing means andto read data therefrom repeatedly because these operations are notperformed like electric circuit but often mechanically done by relativemovement between the readout means and the buffer memory 4.

Furthermore, a significant improvement in accuracy of reading andwriting digital data to and from CD-Rs and other similar media in recentyears has reduced the necessity of error correction by the errorcorrector. Nevertheless, the data in the head portions, which have beenchecked to contain no error, are often subjected to error detection bythe error detector. Consequently, error correction and error detection,which could be processed in parallel in most cases, are processedseparately in time, thereby wasting much time.

The error correction and the error detection are not satisfactory inconsideration of probable higher densities and more rapid readout ofDVDs and other recording media in the future.

In high-speed reproduction performed to check the position of specificimage data or to inspect their contents, it is not always necessary toreproduce image data completely. On the other hand, it is usuallynecessary for data relating to the programs of the CPU to be reproducedin a perfect form even if it takes much time. Thus, error correctionmust be performed at different levels, which have not beensatisfactorily done so far.

Hence, it has been expected to develop an error correction device whichperforms error correction more accurately and faster in accordance withrequired performance levels.

SUMMARY OF THE INVENTION

The present invention has been contrived to solve the aforementionedproblems by paying attention to the following: (1) the data of codewords up to and including the code word subjected to error correction donot change in the error correction by the error corrector; (2) as aresult of (1), the efficiency of the transfer of these data to the errordetector can be improved; (3) the error rate; and (4) the data amount ofeach code word. To be more specific, the present invention has thefollowing structure.

The aspect 1 relates to an error correction device comprising: a buffermemory for storing at least one sector of data (recording data in such amanner as to be able to be read or overwritten) having a structure whereeach of N words (strings) of error correcting code comprises a data unitincluding original image or audio data (main data) etc., an inner codeparity unit, and one error detecting code (data transfer between actualunits are usually done one ECC at a time, but the processes in thepresent aspect can be done one sector at a time); a syndrome calculatingmeans for generating the syndrome for error-contained data read from thebuffer memory; an error correcting means for correcting error-containingdata in the buffer memory by detecting an error position from thesyndrome generated by the syndrome calculating means and by calculatingan error value; an error detecting means for detecting an error inerror-corrected data generated by the error correcting means; a storingmeans composed of a register with a high-speed writing and readingability so as to store mid-term results of an error detecting process inthe error detecting means; a bus control means for controlling datatransfer between the buffer memory, the syndrome calculating means, theerror correcting means, and the error detecting means (preventing acollision between the units in reading, overwriting and otherprocesses); and a system control means for performing various processesfor error correction in predetermined procedures a necessary number oftimes.

The bus control means transfers data from the buffer memory to thesyndrome calculating means and to the error detecting means concurrentlyin code word units until the syndrome calculating means detects anerror-containing code (the data transfer here includes a state wheresome data are left in the buffer memory. Not only in the present aspectbut also in the other aspects, it is considered that some data are leftthere). When the syndrome calculating means detects an error-containingcode, subsequent data in the buffer memory are transferred only to thesyndrome calculating means in code word units. After not only the codeword from which an error-containing code has been detected but also allthe code words in the sector are corrected by the syndrome calculatingmeans, error-corrected data that include the code word from which theerror-containing code has been detected up to and including a final codeword are read from the buffer memory and transferred to the errordetecting means.

The error detecting means executes error detection in parallel withsyndrome calculation done by the syndrome calculating means until thesyndrome calculating means detects an error-containing code, whilestoring the mid-term results of the error detecting process to thestoring means in code word units. After the syndrome calculating meansdetects an error-containing code, the error detecting process issuspended. Then, in the error detection for the data in and after thestring from which the error has been detected, the error-corrected dataare transferred from the buffer memory after the error correction doneby the error correcting means, and error detection is restarted at acode word following the data stored in the storing means.

Consequently, in the error detection done by the error detecting meansafter the error correction, data stored in the storing means are used ascode words before an error-containing code is detected. Thus, themid-term results of an error detecting process are used. This makes itpossible to start an error detecting process at an halfway point afteran error is detected and corrected, thereby greatly reducing the timerequired for error correction. As a result, the error correction devicecan cope with probable higher-speed data reading in the future.

Besides, the bus control means may perform various adjustments in orderto write the error-corrected data to the buffer memory. When an errorcorrecting process is not completed in one time, the system controlmeans may execute error detection and error correction repeatedly in thehorizontal direction and the vertical direction alternately, or datareading from a laser disk or the like may be done again by varying thereading speed. Components provided to realize these functions are wellknown and their description is omitted.

In the aspect 2, data reading from and writing to the buffer memory, anddata transfer are done as DMA transfer. This greatly improves processingspeed.

With recent high-density and high-performing ICs and CPUs, the provisionof the system control unit facilitates the process and control of eachunit, as compared with the process by mere circuits and connectinglines.

The aspect 3 relates to an error correction device comprising: a buffermemory for storing at least one sector of data having a structure whereeach of N strings of error correcting code comprises a data unit, aninner code parity unit, and one error detecting code; a syndromecalculating means for generating syndrome as an equation for errorcorrection for data read from the buffer memory; an error correctingmeans for correcting error-containing data in the buffer memory bydetecting an error position from the syndrome generated by the syndromecalculating means and by calculating an error value; an error detectingmeans for performing error detection repeatedly, one sector at a time,for error-corrected data generated by the error correcting means; a buscontrol means for controlling data transfer between the buffer memory,the syndrome calculating means, the error correcting means, and theerror detecting means; and a system control means for performing variousprocesses for error correction in predetermined procedures a necessarynumber of times.

The bus control means transfers data to be corrected from the buffermemory to the syndrome calculating means and to the error detectingmeans concurrently in code word units until the syndrome calculatingmeans detects an error-containing code. Only when the syndromecalculating means has detected an error-containing code, after the errorcorrection done by the error correcting means for not only the error butalso the subsequent code words, error-corrected data in a sectorcontaining data from which an error-containing code has been detectedare transferred from the buffer memory to the error detecting means.

The error detecting means executes error detection for a code wordtransmitted from the buffer memory, in parallel with the syndromecalculation done by the syndrome calculating means, and only when thesyndrome calculating means has detected an error-correcting code,executes error detection one more time for the error-corrected data.

Consequently, when no error-containing code is detected from one sectorby syndrome calculation, the subsequent error correcting process becomesunnecessary, which can greatly reduce the time required for errorcorrection. Above all, recent improvements in manufacturing techniquesand materials of CD-ROMs reduces the occurrence of minor blemishes dueto manufacturing errors or inappropriate handling of users, so that fewcode words are subjected to error correction. As a result, thesubsequent code words do not need to be processed in most cases, therebyincreasing the effects of the present invention.

The aspect 4 provides the aspect 3 with the same actions and effects asthose which the aspect 2 provides for the aspect 1.

The aspect 5 relates to an error correction device comprising: a buffermemory for storing at least one sector of data having a structure whereeach of N words of error correcting code comprises a data unit, an innercode parity unit, and one error detecting code; a syndrome calculatingmeans for generating syndrome for data read from the buffer memory; anerror correcting means for correcting error-containing data in thebuffer memory by detecting an error position from the syndrome generatedby the syndrome calculating means and by calculating an error value; anerror detecting means for detecting an error, one sector at a time, inerror-corrected data generated by the error correcting means; a storingmeans for storing mid-term results, in code word units, of an errordetecting process in the error detecting means; a bus control means forcontrolling data transfer between the buffer memory, the syndromecalculating means, the error correcting means, and the error detectingmeans; and a system control means for performing various processes forerror correction in predetermined procedures a necessary number oftimes.

The bus control means executes a first transfer where data to becorrected are transferred in code word units from the buffer memoryconcurrently to the syndrome calculating means and to the errordetecting means until the syndrome calculating means detects anerror-containing code. The bus control means suspends the first transferwhen the syndrome calculating means has detected an error-containingcode, and executes a second transfer where the error-corrected code wordis transferred from the buffer memory to the error detecting means afterthe error correction done by the error correcting means for the codeword including an error-containing code. After the completion of thesecond transfer, the first transfer for subsequent code words isresumed. This process is executed every time an error-containing code isdetected.

The error detecting means, until the syndrome calculating means detectsan error-containing code, executes a first error detection where errordetection is performed for a code word transmitted from the buffermemory in parallel with the syndrome calculation done by the syndromecalculating means, while storing mid-term results of the error detectionin code word units to the storing means. After the syndrome calculatingmeans detects an error-containing code, the error detecting meansexecutes error detection for code words whose errors have been detectedand corrected by the error correcting means, and stores them in the nextposition in the storing means. After the completion of the errordetection for the code words, the first error detection is resumed.These processes are repeated every time the syndrome calculating meansdetects an error-containing code.

Thus, by exclusively re-transferring the data of the code word fromwhich an error-containing code is detected and corrected to the errordetector, the sequential process of error-containing code detection,error correction, and error detection can be executed in parallel,thereby greatly reducing the time required for error correction.

The aspect 6 provides the aspect 5 with the same actions and effects asthose which the aspect 2 provides for the aspect 1.

The aspect 7 relates to an error correction device comprising; a buffermemory for storing at least one ECC block of data (one ECC block isenough in the present aspect) having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction, for example, sectoras a unit, are subjected to error correction a syndrome calculatingmeans for generating syndrome for data read from the buffer memory; anerror correcting means for correcting error-containing data in thebuffer memory by detecting an error position from the syndrome generatedby the syndrome calculating means and by calculating an error value; anerror detecting means for detecting an error in error-corrected datagenerated by the error correcting means; a bus control means forcontrolling data transfer between the buffer memory, the syndromecalculating means, the error correcting means, and the error detectingmeans; and a system control means for performing various processes forerror correction in predetermined procedures a necessary number oftimes.

In the system control means, a first-time error correction sub meansreads data from the buffer memory in the same direction as calculationfor an error detecting code as a first-time error correction; transfersthe read data to the syndrome calculating means and to the errordetecting means concurrently until the syndrome calculating meansdetects an error-containing code; makes the syndrome calculating meansexecute syndrome calculation and the error detecting means execute errordetection in parallel; makes the error correcting means execute errorcorrection when the syndrome calculating means has detected anerror-containing code; and makes one or both of the syndrome calculatingmeans and the error correcting means provide the system control meanswith information which designates a code word containing theerror-containing code.

The even-numbered error correction sub means reads a code word in thedifferent direction from a preceding odd-numbered error correction;transfers the code word to the syndrome calculating means and to theerror detecting means concurrently until the syndrome calculating meansdetects an error-containing code; makes the syndrome calculating meansexecute syndrome calculation and the error detecting means execute errordetection in parallel; makes the error correcting means execute errorcorrection when the syndrome calculating means detects anerror-containing code; and makes the error correcting means provide thesystem control means with information which designates the position ofthe error-containing code in an error correcting code word obtained inthe error correction.

The non-error range designating sub means designates, one sector at atime, a range from which an error-containing code has not been detectedat the odd-numbered error correction or the subsequent even-numberederror correction, based on the information that designates the code wordincluding the error-containing code and the information that designatesthe position of the error-containing code in the error correcting codeword.

The odd-numbered error correction sub means, as an odd-numbered errorcorrection in the third-time or later error correction, providesconcurrently the syndrome calculating means and the error detectingmeans with a code in the same direction as in the previous odd-numberederror correction except for a sector in one ECC block which has beendesignated by the non-error range designating sub means as the rangefrom which an error-containing code has not been detected in and beforethe preceding even-numbered error correction until the syndromecalculating means detects an error-containing code; makes the syndromecalculating means execute syndrome calculation and the error detectingmeans execute error detection in parallel, while using the processingresults of sectors whose results in previous error detection andcorrection have been corrected; makes the error correcting means executeerror correction when the syndrome calculating means detects anerror-containing code; and makes one of the syndrome calculating meansand the error correcting means provide the system control means withinformation which designates the code word including theerror-containing code.

The number-of-times control sub means repeats the odd-numbered errorcorrection and the even-numbered error correction a predetermined numberof times.

In the aspect 8, the number-of-times control sub means repeats the errorcorrection three times at most because it would be meaningless to repeaterror correction more than three times under the developed technology inthe recent years. If error correction were not to be complete in threetimes, data might be read again at different speed, or correctionalgorithm might be changed. In case of image data, which are notadversely affected by minor noises, might be transferred downstream asthey are, or data at the same position in the preceding scene might beused instead. In other aspects, the same process will be done if errorcorrection is not complete after several times of correction.

In the aspect 9, the error correction device of the aspect 7 or 8further comprising a storing means for storing mid-term results, in codeword units, of each code word from which no error has been detected inthe error detecting process done by the error detecting means until thesyndrome calculating means detects an error-containing code.

The non-error range designating sub means is a non-error sector codeword range designating sub means for designating, in code word units ofa sector, a range from which an error-containing code has not beendetected in the odd-numbered error correction or the subsequenteven-numbered error correction, based on the information that designatesthe code word including the error-containing code and on the informationthat designates the position of the error-containing code in the errorcorrecting code word in an ECC to be processed.

The odd-numbered error correction sub means is an odd-numbered errorcorrection sub means with mid-term results for, in the third-time orlater odd-numbered error correction, making the bus control means starta concurrent data transfer not at the head but at the code word of thesector from which an error-containing code has been detected, based onthe information designated by the non-error sector code word rangedesignating sub means; for making the syndrome calculating means startsyndrome calculation at the code word; and for making the errordetecting means start error detection at a code word somewhere in themiddle of the sector by using contents stored in the storing means as aninitial value.

In the aspect 10, in the error correction devices of the aspects 7 and 8further comprising a sector-basis storing means for storing mid-termresults, on a sector-by-sector basis, in code word units, of each codeword from which no error has been detected in the error detectingprocess done by the error detecting means, until the syndromecalculating means detects an error-containing code. As a result, thesame action as in the aspect 9 is done in code word units of eachsector.

In the aspect 11, in the error correction devices of the aspects 7 and 8further comprising a sector-group-basis storing means for storingmid-term results, on a sector-group-by-sector-group-basis, in code wordunits, of each code word from which no error has been detected in theerror detecting process done by the error detecting means until thesyndrome calculating means detects an error-containing code. As aresult, the same action as in the aspect 9 is done in code word units ofeach sector.

In the aspects 12-15, in the error correction devices of the aspects 1,2, 5, 6, 7, and 8, error correction is performed in parallel (by meansof so-called pipeline processing) for data in a plurality of ECC blockseach having a structure where a plurality of error correcting code wordseach comprising a data unit and a parity unit are arranged in verticaldirection and horizontal direction so as to repeat error correction aplurality of number of times, and where predetermined data composed of apredetermined number of code words in the vertical direction or thehorizontal direction, for example a sector as a unit, are subjected tothe error correction.

The buffer memory is a plural-ECC-block-division buffer memory forstoring a plurality of ECC blocks to be processed in parallel byassigning addresses either sequentially or like a circle conceptually inpipeline processing, and for reading data in the same manner.

The storing means for storing mid-term results of an error detectingprocess generated by the error detecting means is an ECC-block-divisionstoring means for storing the plurality of ECC blocks on ablock-by-block basis.

In the system control means, the means-basis ECC block pipelineprocessing notification sub means transmits one or more ECC blocks whichhave been subjected to error correction downstream; stores one or moreECC blocks to be processed next at a predetermined address such as theaddress of the ECC block transferred downstream by overwriting them inthe plural-ECC-block-division buffer memory; and makes the storage knownto the bus control means, the syndrome calculating means, the errordetecting means, and the error correcting means. To be more specific,the table showing processing targets referred to by each means arere-written. Besides, in the downstream units, transferred ECC blocks maybe rearranged in accordance with the original order.

The means-basis ECC block recognition sub means recognizes a datatransfer from the bus control means to the syndrome calculating means,to the error detecting means, and to the error correcting means forerror detection and error correction; recognizes the error correctiondone by the error correcting means; recognizes writing oferror-corrected data to the plural-ECC-block-division buffer memory doneby the bus control means; recognizes ECC blocks in process when theerror detecting means stores mid-term results to theplural-ECC-block-division storing means, and selects ECC blocks to beprocessed.

The ECC block notification sub means in sub means-basis pipelineprocessing notifies the first error detecting sub means, theeven-numbered error correction sub means, the odd-numbered errorcorrection sub means, the number-of-times control sub means, and the DMAtransfer instruction sub means contained in the system control meansthat the error-corrected ECC blocks have been transmitted downstream andnew ECC blocks to be processed have been stored in theplural-ECC-block-division buffer memory, and further notifies these samesub means contained in the system control means of the ECC blocks whichare in process therein.

In the aspects 16-19, in the error correction devices of aspects 1, 2,5, 6, 7, 8, 9, 10, and 11, error correction is performed in parallel fora plurality of ECC blocks according to pipeline processing as follows.

The buffer memory is an ECC-block-basis buffer memory for storing andreading, on a block-by-block basis, ECC blocks to be processed inparallel.

The storing means for storing mid-term results of an error detectingprocess generated by the error detecting means is an ECC-block-and-codeword-division storing means for storing ECC blocks in process on ablock-by-block basis, and code words in each ECC block, in each sector,or in each sector group, on a string-by-string basis.

In the system control means, the means-basis ECC block pipelineprocessing notification sub means transmits ECC blocks which have beensubjected to error correction downstream; stores ECC blocks to beprocessed next to the ECC-block-basis buffer memory; and makes thestorage known to the bus control means, the syndrome calculating means,the error detecting means, and the error correcting means.

The means-basis ECC block code word recognition sub means selects codewords of the ECC blocks to be processed, in accordance with the contentsstored in the ECC-block-and-code word-division storing means, incontrolling a data transfer from the bus control means to the syndromecalculating means, to the error detecting means, and to the errorcorrecting means for error detection and error correction; incontrolling the error correction done by the error correcting means; incontrolling writing of error-corrected data to the ECC-block-basisbuffer memory done by the bus control means; in storing mid-term resultsto the ECC-block-and-code word-division storing means by the errordetecting means.

The ECC block code word recognition sub means in sub means-basispipeline processing makes the first error detecting sub means, theeven-numbered error correction sub means, the odd-numbered errorcorrection sub means, the number-of-times control sub means, and the DMAtransfer instruction sub means in case equipped in the system controlmeans recognize that the error-corrected ECC blocks have beentransmitted downstream and new ECC blocks to be processed have beenstored in the ECC-block-basis buffer memory, and further makes thesesame sub means contained in the system control means recognize the ECCblocks and the code words which are to be processed therein.

In order to facilitate the pipeline processing and the use of themid-term results of error detection, the system control means has aconceptual list of each ECC block, each sector and each code word ineach ECC block to be processed.

While in the error correction devices of the aspects 1, 2, 5, 6, 7, 8,9, 10, and 11, the pipeline processing of the aspects 12-15 makes databe stored in descending order of ECC blocks in the buffer memory andtransmitted downstream block by block after error correction is done asa rule. In contrast, in the aspects 20-23, several ECC blocks arecollectively stored in the buffer memory in descending order andcollectively transmitted downstream after error correction.

The collective data transfer is useful, for example, in avideo-on-demand system where image data are transmitted in extremelyshort time units in order to transmit the same movie or the like to asmany viewers as possible approximately at the same time. To be morespecific, error correction is executed scene by scene, and if completeerror correction is impossible, the CPU can correct data of a scene byextrapolation with the data prior to and subsequent to the scene.

The collective data transfer is also useful when discrete data for onescene is subjected to error correction in high-speed reproduction forretrieval. In this case, it goes without saying that data for one sceneare recognized in compliance with recording in CPU or the like orcommunication regulations (protocol)(for example, EOP signals).

In the error correction devices of the aspects 20-23, the mid-termresults of previous error calculation are used in ECC units in and afterthe second time error correction. In contrast, in the aspects 24-27, themid-term results are used in predetermined data units such as one sectorat a time or one sector group at a time. Therefore, the aspects 24-27provide the aspects 23-29 with the same advantages and effects that theaspects 16-19 provide to the aspects 12-15.

The aspect 28 relates to an error correction device which performs errorcorrection for data in ECC blocks each having a structure where errorcorrecting code words each comprising a data unit and a parity unit arearranged in vertical and horizontal directions so as to realize repeatederror correction, and predetermined data composed of a predeterminednumber of code words in the vertical or horizontal direction (data inthe horizontal direction are referred to as sector) are as one unitsubjected to error correction, and which also perform syndromecalculation and error detection in parallel with a storage ofdemodulated codes in a buffer memory.

The first syndrome calculating means performs syndrome calculation ofdata in the buffer memory.

The first error detecting means pairs up with the first syndromecalculating means and performs error detection concurrently therewith.

The second syndrome calculating means performs syndrome calculation ofdemodulated codes without the buffer memory.

The second error detecting means pairs up with the second syndromecalculating means, and performs error detection concurrently therewith.

The storing means stores the right portions of mid-term results ofcalculations of the first error detecting means and the second errordetecting means in descending order of code words and sectors.

The buffer memory parallel transfer means transfers data transmittedfrom upstream to the second syndrome calculating means and to the seconderror detecting means in parallel with storage of the data in the buffermemory until the second syndrome calculating means detects anerror-containing code.

The error-detecting-means switch means provides the storing means withthe mid-term results of the calculation by the second error detectingmeans of code words until the error-containing code is detected.

The error correcting means performs error correction after one of thefirst error detecting means and the second error detecting means detectsan error-containing code word, so as to perform error correction of datain the buffer memory directly or indirectly.

The parallel transfer means transfers data stored in the buffer memory,starting at a code word which is not stored in the storing means to thefirst syndrome calculating means and to the first error detecting means,on and after the second-time error correction in the same direction,before the first syndrome calculating means detects an error-containingcode.

The second-time onward detecting-processed data use means performs errordetection of the subsequent code words by using the mid-term resultsstored in the storing means, on and after the second-time errordetection in the same direction done by the second error detectingmeans.

While the results of previous calculation are used in ECC units in andafter the second-time error correction in the aspect 28, it is done inpredetermined data units such as one sector at a time or one sectorgroup at a time in the aspect 29. Therefore, the aspect 29 has the sameadvantages as those which the aspects 24-27 provide for the aspects20-23.

The aspect 30 is a combination of the aspects 20-23 or the aspects 24-27and the aspect 28 or 29. Therefore, demodulated data are subjected toerror correction before being stored in the buffer memory, and the datastored in the buffer memory are subjected to error correction inpipeline processing. Furthermore, the mid-term results in the previouserror calculation are used either one ECC, one sector, or one sectorgroup at a time.

Therefore, the syndrome calculating means or the error calculatingmeans, which directly executes syndrome calculation of demodulated data,executes syndrome calculation of the data in the buffer memory after allof the demodulated predetermined data are stored in the buffer memory.This further increases the speed of error calculation, and is useful toexecute a high-speed processing of data stored in media that have beenunder poor storage conditions for a long time period.

In the aspects 31-50, there are two buffer memories, and when data inone buffer memory are subjected to error correction, a predeterminedamount of data such as in subsequent sectors or in ECC block units arewritten to the other buffer memory. While the error-corrected data areread from one buffer memory in order to be transmitted downstream,subsequent data in the other buffer memory are already subjected toerror correction. For this, the accessed buffer memory switch meansdirects the buffer memory to be accessed to the bus control means andthe system control means. As a result, the effects of high-speed errorcorrection with the mid-term results are exerted more effectively.

When it is difficult to provide error correction for the data read anddemodulated at normal speed, in a device where reading is done again byvarying the speed, the data in the same sector as the sector whose dataare read again are stored in place of or after the data of thesubsequent sector, and in the former case, the data are subjected toerror correction later, and in the latter case, these data are replacedafter error correction.

The alternating switch between two buffer memories and one-sectorshifting of data in reading them again are not hard techniques in termsof programs, circuits, or hardware, so that their description will beomitted.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the data format for one sector of a DVD.

FIG. 2 shows the data format for one block including ECCs of a DVD.

FIG. 3 shows the structure of a prior art error correction device.

FIG. 4 shows the procedure (flow chart) of the processing of the priorart error correction device.

FIG. 5 shows the structure (block diagram) of the error correctiondevice of Embodiment 1 of the present invention.

FIG. 6 shows the procedure of the processing of the error correctiondevice.

FIG. 7 shows the structure of the error correction device of Embodiment2 of the present invention.

FIG. 8 show the procedure of the processing of the error correctiondevice.

FIG. 9 shows the structure of the error correction device of Embodiment3 of the present invention.

FIG. 10 shows the procedure of the processing of the error correctiondevice.

FIG. 11 shows the structure of the error correction device of Embodiment4 of the present invention.

FIG. 12 shows the structure of the error correction device of Embodiment5 of the present invention.

FIG. 13 explains the error-containing codes and the data transfer rangeof the error correction device of the embodiment.

FIG. 14 shows the procedure of the processing of the error correctiondevice.

FIG. 15 shows the structure of the error correction device of Embodiment6 of the present invention.

FIG. 16 is a timing chart illustrating the operation of the errorcorrection device of the embodiment

FIG. 17 explains the error-containing codes and the data transfer rangeof the error correction device of the embodiment.

FIG. 18 shows the structure of the error correction device of Embodiment7 of the present invention.

FIG. 19 conceptually shows the effects of the pipeline processing in theerror correction device of the embodiment.

FIG. 20 shows the structure of the error correction device of Embodiment8 of the present invention.

FIGS. 21A and 21B conceptually show the reference tables stored andmanaged by the control unit in the error correction device of theembodiment in order to facilitate pipeline processing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described as follows based on itsembodiments.

Embodiment 1

The present embodiment differs from the prior art in that a mid-termresult register is provided and that an error-containing code detectionsignal and an error-containing code word signal are entered to thesystem control unit from the syndrome calculator.

FIG. 5 shows the structure of the error correction device of the presentembodiment. In the device, the system control unit 1, the DMA controlunit 2, the bus control unit 3, the buffer memory 4, the syndromecalculator 5, the error corrector 6, and the error detector 7, which arebasically identical to the components in the prior art, are referred towith the same reference numbers. (In the present and the followingembodiments, the identical components are referred to with the samereference numbers unless they must be distinguished. This holds true forsignals).

The same as in the prior art device, the bus control device 3, thebuffer memory 4, the syndrome calculator 5, the error corrector 6, andthe error detector 7 are connected via the data bus 11.

The DMA command 12, the DMA request 13, the buffer memory access signal14, the syndrome supply signal 15, the syndrome 16, the access requestsignal 17, the error corrector access signal 18, the correctioncompletion signal 19, the error detector data supply signal 20, and theerror detection signal 21 are also basically identical to those in theprior art device, so they are referred to with the same referencenumbers.

The mid-term result register 8, which is connected with the errordetector 7, stores the mid-term results of the error detecting processdone in the error detector 7. The error-containing code detection signal22, which indicates that an error-containing code word has been detectedby the syndrome calculator 5, is transmitted to the system control unit1 and to the error detector 7. The error-containing code word signal 23,which indicates in which code word the error is detected by the syndromecalculator 5, is transmitted to the system control unit 1.

The behavior of the error correction device thus structured will bedescribed as follows, with reference to FIG. 6.

FIG. 6 shows the procedure of horizontal error correction in one sector.

Step (b-1): the same process as at step (a-1) in the prior art isperformed except that not only the syndrome calculator 5 but also theerror detector 7 are provided with instructions to transfer data.

Step (b-2): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the syndrome calculator 5 and to the error detector 7.

Step (b-3): the bus control unit 3 puts the data bus 11 in commission,and outputs the buffer memory access signal 14 to the buffer memory 4 toread the data therefrom. The bus control unit 3 then outputs thesyndrome data supply signal 15 and the error detector data supply signal20 to the syndrome calculator 5 and the error detector 7, respectively,so as to supply the data read from the buffer memory 4 to the syndromecalculator 5 and to the error detector 7.

Step (b-4): the syndrome calculator 5 performs error-containing codedetection for every transferred code word, and outputs the syndrome 16to the error corrector 6. When an error-containing code word isdetected, the syndrome calculator 5 outputs the error-containing codedetection signal 22 to the error detector 7 and the system control unit1, and also provides the system control unit 1 with the error-containingcode word signal 23 indicating from which code word the error has beendetected.

On the other hand, the error detector 7 also executes an error detectingprocess every code word. Only when the detection of an error-containingcode is not informed by the error-containing code detection signal 22,the error detector 7 stores the mid-term results of the error detectionin every code word to the mid-term result register 8 whose response isquicker than memory. When the detection of the error-containing code hasbeen informed, the error detector 7 does not perform error detection forthe subsequent code words including the code word informed.

Step (b-5): the same process as at step (a-5) is performed.

Step (b-6): after putting the data bus 11 in commission, the bus controlunit 3 outputs the buffer memory access signal 14 to the buffer memory 4to read error-containing data therefrom. Then, the bus control unit 3outputs the error corrector access signal 18 to the error corrector 6 tosupply the data thereto.

Step (b-7): the same process as at step (a-7) is performed.

Step (b-8): after putting the data bus 11 in commission, the bus controlunit 3 reads the error-corrected data from the error corrector 6 andoverwrites the data in the buffer memory 4. When error correction forone sector is complete, the error corrector 6 transmits the correctioncompletion signal 19 to the system control unit 1.

The above step (b-4) is executed in parallel with steps (b-5) through(b-8) like a pipeline.

Step (b-9): in order to check to see that the corrected data contain nomore error, the system control unit 1 transmits the DMA command 12 tothe DMA control unit 2 so as to provide instructions to transfer thedata from the buffer memory 4 to the error detector 7. The systemcontrol unit 1 make the data transfer be started from the code wordindicated by the error-containing code word signal 23 outputted at thesame time as the error-containing code detection signal 22 firstoutputted from the syndrome calculator 5 at step (b-4).

Step (b-10): the same process as at step (a-10) is performed.

Step (b-11): after putting the data bus 11 in commission, the buscontrol unit 3 outputs the buffer memory access signal 14 to the buffermemory 4 to read the data therefrom. Then, the bus control unit 3outputs the error detector data supply signal 20 to the error detector 7so as to supply the data read from the buffer memory 4.

Step (b-12): while using the mid-term results of error correction storedin the mid-term result register 8 as the initial value, the errordetector 7 executes error detection for the transferred subsequent data,and informs the system control unit 1 of the presence or the absence ofan error by transmitting the error detection signal 21.

When an error-containing code is not detected in the syndrome calculator5 at step (b-4), the error correcting operations between steps (b-5) and(b-8) are performed in parallel with step (b-4) for code words indescending order of stream; however, error correction for the data onthe buffer memory 4 is not performed because an error-containing codehas not been detected. The error detecting process done by the errordetector 7 is complete at step (b-4), and the error detection signal 21is transmitted to the system control unit 1 so as to indicate whether anerror has been detected or not. In this case, steps (b-9) through (b-12)are not executed.

Through these steps, the horizontal error correction for one sector iscomplete. In the same manner, horizontal error correction for thesubsequent 15 sectors is executed so as to complete the horizontal errorcorrection for one block. If no error is detected from all sectors, theerror correcting operation is complete; if there is an error detectedeven from one sector, the next process including vertical errorcorrection will be executed.

As described hereinbefore, in the present embodiment, data aretransferred from the buffer memory 4 not only to the syndrome calculator5 but also to the error detector 7 at the same time, and until anerror-containing code is detected by the syndrome calculator 5, errordetection in the error detector 7 is executed concurrently with syndromecalculation. In the error detection performed after the error correctionof the error corrector 6, the mid-term results of the error detectionbefore the detection of the error-containing code transmitted to andstored in the mid-term result register 8 are used. This eliminates theneed for all data to be transferred from the buffer memory 4 to theerror detector 7. In addition, the error detecting process can start ata halfway point. Hence, the time required for error correction can begreatly reduced.

To be more specific, when the error rate is 0.05%, 2048-byte main datacontain one error on the average, which means that the error is likelyto arise around the central code word on the average of 12 code words inthe horizontal direction. Therefore, the mid-term results register 8 hasthe first 6 code words, and only the remaining 6 code words can betransferred after error correction. Thus, the time required for errordetection is also reduced approximately in half.

Embodiment 2

The present embodiment differs from the prior art in that the syndromecalculator 5 provides the system control unit 1 with an error-containingcode sector detection signal 22, which indicates that anerror-containing code word has been detected from the sector.

FIG. 7 shows the structure of the error correction device of the presentembodiment.

The behavior of the error correction device of the present embodimentwill be described as follows with reference to the procedure ofhorizontal error correction in one sector shown in FIG. 8.

Step (c-1): the same process as at step (b-1) in Embodiment 1 isperformed.

Step (c-2): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the syndrome calculator 5 and to the error detector 7.

Step (c-3): the bus control unit 3 puts the data bus 11 in commission,and outputs the buffer memory access signal 14 to the buffer memory 4.The bus control unit 3 then outputs the syndrome data supply signal 15and the error detector data supply signal 20 to the syndrome calculator5 and the error detector 7, respectively, so as to supply the data readfrom the buffer memory 4 to the syndrome calculator 5 and to the errordetector 7 (same as at step (b-3) in the first embodiment).

Step (c-4): the syndrome calculator 5 performs error-containing-codedetection every transferred code word, and outputs the syndrome 16 tothe error corrector 6. When an error-containing code word is detected inone sector, the syndrome calculator 5 outputs the error-containing codesector detection signal 22 to the system control unit 1. On the otherhand, the error detector 7 also executes an error detecting process forthe data transferred.

Step (c-5): the same process as at step (a-5) of the prior art isperformed.

Step (c-6): after putting the data bus 11 in commission, the bus controlunit 3 outputs the buffer memory access signal 14 to the buffer memory 4to read data therefrom. Then, the bus control unit 3 outputs the errorcorrector access signal 18 to the error corrector 6 to supply the dataread from the buffer memory 4 thereto.

Step (c-7): the same process as at step (a-7) in the prior art isperformed.

Step (c-8): the same process as at step (b-8) in the first embodiment isperformed.

Step (c-4) is executed in parallel with steps (c-5) through (c-8) like apipeline.

Step (c-9): the same process as at step (a-9) in the prior art isperformed.

Step (c-10): the same process as at step (a-10) in the prior art isperformed.

Step (c-11): the same process as at step (b-11) in the first embodimentis performed.

Step (c-12): the same process as at step (a-12) in the prior art isperformed.

When an error-containing code is not detected in one sector by thesyndrome calculator 5 at step (c-4), the error correcting operationsbetween steps (c-5) and (c-8) are performed in parallel with theoperation at step (c-4); however, error correction for the data on thebuffer memory 4 is not performed because an error-containing code hasnot been detected.

The error detecting process done by the error detector 7 is complete atstep (c-4), and the error detection signal 111 is transmitted to thesystem control unit 1 so as to inform whether an error has been detectedor not. In this case, steps (c-9) through (c-12) are not executed.

Through these steps, the horizontal error correction for one sector iscomplete. In the same manner, horizontal error correction for thesubsequent 15 sectors is executed so as to complete the horizontal errorcorrection for one block. If no error is detected from all sectors, theerror correcting operation is complete; if there is an error detectedeven from one sector, the next process including vertical errorcorrection will be executed.

As described hereinbefore, in the present embodiment, data aretransferred from the buffer memory 4 not only to the syndrome calculator5 but also to the error detector 7 at the same time, and the errordetector 7 executes error detection concurrently with syndromecalculation. If an error-containing code is not detected in one sectorin the syndrome calculation, the subsequent operations becomeunnecessary, which greatly reduces the time required for errorcorrection. Hence, the present invention will become more significantwhen probable technological development in the future reduces the errorrate.

Unlike Embodiment 1, the mid-term result register 8, which is moreexpensive than memory, becomes unnecessary.

Embodiment 3

The present embodiment differs from the prior art in that the syndromecalculator 5 outputs the error-containing code detection signal 22,which indicates that an error-containing code word has been detected, tothe DMA control unit 2 and to the error detector 7; the error corrector6 outputs the error-containing code word signal 23 to the DMA controlunit 2 and to the error detector 7; and that the mid-term resultregister 8 is provided.

FIG. 9 shows the structure of the error correction device of the presentembodiment.

In FIG. 9, in response to the output of the error-containing codedetection signal 22, the error detector 7 suspends an error detectingprocess, and the DMA control unit 2 suspends a data transfer from thebuffer memory 4 to the syndrome calculator 5. The error corrector 6outputs an one-code word error correction completion signal 23 when itcompletes error correction for one code word.

FIG. 10 shows the procedure of horizontal error correction in one sectorof the error correction device of the present embodiment.

The behavior of the error correction device will be described as followswith reference to FIG. 10.

Step (d-1): the same process as at step (c-1) of Embodiment 2 isperformed.

Step (d-2): the same process as at step (c-2) of Embodiment 2 isperformed.

Step (d-3): the same process as at step (b-3) of Embodiment 1 isperformed.

Step (d-4): the syndrome calculator 5 performs error-containing codedetection for every transferred code word, and outputs the syndrome 16to the error corrector 6. When an error-containing code word isdetected, the syndrome calculator 5 outputs the error-containing codedetection signal 22 to the error detector 7 and to the DMA control unit2. On the other hand, the error detector 7 also executes error detectionfor each code word. Only when the error-containing code detection signal22 has not been outputted, the mid-term results of error detection foreach code word are stored in the mid-term result register 8. When thedetection of error-containing code has been informed by theerror-containing code detection signal 22, the error detector 7 suspendsan error detecting process. At the same time, the syndrome calculator 5informs the DMA control unit 2 of the detection of an error-containingcode. The DMA control unit 2 suspends an output of the DMA request 13 tothe bus control unit 3. The bus control unit 3 suspends a data transferfrom the buffer memory 4 to the syndrome calculator 5.

Step (d-5): the same process as at step (a-5) in the prior art isperformed.

Step (d-6): the same process as at step (b-6) in the first embodiment isperformed.

Step (d-7): the same process as at step (a-7) in the prior art isperformed.

Step (d-8): after putting the data bus 11 in commission, the bus controlunit 3 reads the error-corrected data from the error corrector 6 andoverwrites the data in the buffer memory 4. When error correction forone code word is complete, the error corrector 6 transmits the one-codeword error correction completion signal 23 to the DMA control unit 2 andto the error detector 7.

Step (d-9): in response to the output of the one-code word errorcorrection completion signal 23, the DMA control unit 2 outputs the DMArequest 13 to the bus control unit 3 so as to request the transfer ofthe error-corrected code word from the buffer memory 4 to the errorcorrector 7.

Step (d-10): after putting the data bus 11 in commission, the buscontrol unit 3 outputs the buffer memory access signal 14 to the buffermemory 4 to read the data therefrom. Then, the bus control unit 3outputs the error detector data supply signal 20 to the error detector 7so as to supply the data read from the buffer memory 4.

Step (d-11): while using the mid-term results of error correction storedin the mid-term result register 8, the error detector 7 executes errordetection for the transferred subsequent data up to and including thefinal code word.

Step (d-12): upon completion of the DMA transfer to the error detector7, the DMA control unit 2 resumes the output of the DMA request 13transferring the subsequent code words to the syndrome calculator 5 andto the error detector 7. The bus control unit 3 executes a data transferfrom the buffer memory 4 to the syndrome calculator 5 and to the errordetector 7.

The operations at steps (d-4) through (d-12) are repeated until errorcorrection for one sector is complete.

When the error correction for one sector is complete, the errorcorrector 6 outputs the error correction completion signal 19 to thesystem control unit 1, and the error detector 7 informs the systemcontrol unit 1 whether an error has been detected or not by transmittingthe error detection signal 21.

When an error-containing code has not been detected in the syndromecalculator 5 at step (d-4), the error correcting operations betweensteps (d-5) and (d-8) are executed concurrently with the operation atstep (d-4); however, the error correcting operation for data on thebuffer memory 4 and the DMA transfer are not suspended because anerror-containing code has not been detected. The error detection of theerror detector 7 is complete at step (d-4), and it is informed to thesystem control unit I by transmitting the error detection signal 21 thatno error has been detected. In this case, steps (d-9) through (d-12) arenot executed.

Through these steps, horizontal error correction for one sector iscomplete. In the same manner, horizontal error correction is executedfor the subsequent 15 sectors so as to complete the horizontal errorcorrection for one block. If no error is detected from all sectors, theerror correcting operation is complete; if there is an error detectedeven from one sector, the next process including vertical errorcorrection will be executed.

As described hereinbefore, in the present embodiment, data aretransferred from the buffer memory 4 not only to the syndrome calculator5 but also to the error detector 7 at the same time, and until thesyndrome calculator 5 detects an error-containing code, the errordetector 7 executes error detection concurrently with syndromecalculation. If an error-containing code is detected by the syndromecalculator 5, the syndrome calculation is suspended, and theerror-containing code is corrected by the error corrector 6. Then, thedata are transferred to the error detector 7 so as to be subjected toerror detection. After the error detection, the subsequent code wordsare transferred to the syndrome calculator 5 and to the error detector 7where syndrome calculation and error detection are executed in parallel.

Thus, when an error-containing code word has been detected, theerror-corrected data of the code word can be exclusively re-transferredto the error detector 7 so as to execute a series of processes includingerror-containing code detection, error correction, and error detectionin parallel, thereby greatly reducing the time required for errorcorrection.

Embodiment 4

The present embodiment provides two buffer memories in order to reducethe time required for reading and writing data; while data are beingread from or written to one of the buffer memories, data in the otherbuffer memory are subjected to error correction.

The structure of the main part of the error correction device of thepresent invention is shown in FIG. 11. The error correction devicecomprises a downstream processing unit 9 composed of a transfer controldevice and the like, an upstream processing unit 10 composed of ademodulator and the like, a first buffer memory 41 provided with anoverwrite unit and a readout unit, and a second buffer memory 42provided with an overwrite unit and a readout unit. The device furthercomprises a buffer switch control unit 101, a buffer data transfercontrol unit 102, and an initial setting unit 103 which are arranged inthe system control unit 1. The solid lines indicate the flow of digitaldata, and the dot lines indicate the flow of control signals.

The action of each unit will be described as follows.

When error correction begins, the initial setting unit 103 writes thedata of the first sector to the first buffer memory 41 and the data ofthe second sector to the second buffer memory 42. The initial settingunit 103 also sets the flag in the buffer switch control unit 101 at 1,and provides the buffer switch control unit 101 and the buffer datatransfer control unit 102 with instructions for the setting.

The buffer switch control unit 101, when the error correction begins,refers to the flag, and connects the first buffer memory 41 with thesyndrome calculator 5, the error detector 7, and the like. As the errorcorrection proceeds, the buffer switch control unit 101 refers to theflag every time it receives a transfer signal from the buffer datatransfer control unit 102 to switch the buffer memories, and write datareceived from the upstream processing unit 10 to the correspondingbuffer memory every time the flag is switched.

Every time error correction for one sector is complete, the buffer datatransfer control unit 102 switches circuits so as to transfer dataeither in the first buffer memory 41 or the second buffer memory 42 tothe downstream processing unit 9; transmits a transfer signal to thebuffer switch control unit 101 at the same time; and makes the flagswitch unit set the flag between at 1 and at 2 alternately.

When the error correction for one sector is complete, the data in thebuffer memory that has been in process is flown to the downstreamprocessing unit 9. On the other hand, the data to be subjected to thenext error correction are already written in the other buffer memory bythe buffer switch control unit 101, which quickens error correction.

Embodiment 5

While in Embodiments 1 to 3, the mid-term result register 8 is shared byall sectors, in the present embodiment each of the 16 sectors of one ECCblock is provided with a mid-term result register, considering that dataare often transferred in one-ECC increments in the actual errorcorrection, which may include vertical error correction.

FIG. 12 shows the structure of the error correction device 100 of thepresent embodiment. In FIG. 12, an optical disk 201 is driven by aspindle motor 202, and an optical head 203 reads data stored in theoptical disk 201 and outputs them to an amplifier 204. An reception code29 is read out in the same direction as the horizontal (inner code)error correction and entered to the error correction device 100. In thedevice 100, the reception code 29 is entered to a demodulator 10 and thedemodulated code is stored in the buffer memory 4 by a demodulation codeenter signal 25 outputted from the bus control unit 3.

A transfer control unit 9 transmits an error-corrected code 30 read fromthe buffer memory 4 to an external unit 205 such as a personal computer.The data transfer to the external unit 205 is performed by the buffermemory access signal 14 and a demodulation code enter signal 25, whichare outputted by the bus control unit 3.

As shown in FIG. 12, the error detector 7 is provided with 16 mid-termresult registers 801, 802, . . . 816 for 16 sectors in one ECC block.

FIG. 13 shows error-containing codes in the sectors and the datatransfer range in error detection of the present embodiment.

The behavior of the error correction device 100 of the presentembodiment thus structured will be described with reference to FIGS. 12,13, and 14.

Step (e-1): in order to perform error correction, the system controlunit 1 outputs the DMA command 12 to the DMA control unit 2 so as toprovide instructions to transfer data equivalent to one code word in thehorizontal direction×13 times, or one sector from the buffer memory 4 tothe syndrome calculator 5 and to the error detector 7.

Step (e-2): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the syndrome calculator 5 and to the error detector 7.

Step (e-3): the bus control unit 3 puts the data bus 11 in commission,and outputs the buffer memory access signal 14 to the buffer memory 4.The bus control unit 3 then outputs the syndrome data supply signal 15and the error detector data supply signal 20 to the syndrome calculator5 and the error detector 7, respectively, so as to supply the data readfrom the buffer memory 4 to the syndrome calculator 5 and to the errordetector 7.

Step (e-4): the syndrome calculator 5 calculates a syndrome 16 of thetransferred horizontal code word, and outputs the syndrome 16 to theerror corrector 6. If the code word contains an error-containing code,or if the syndrome is not zero, the syndrome calculator 5 outputs theerror-containing code detection signal 22 to the error corrector 7 andto the system control unit 1. The syndrome calculator 5 also providesthe system control unit 1 with the error-containing code word signal 23indicating the code word from which an error has been detected.

At the same time, the error detector 7 executes an error detectingprocess. Prior to the error detection, the mid-term results of the EDCsin the preceding code words stored in the corresponding one of themid-term result registers 801-816 are reloaded. If the syndrome is zerowhen the transfer of each code word is over, the mid-term results of theEDCs are stored in the corresponding mid-term result register again.When the syndrome is not zero, on the other hand, the mid-term resultsof the EDCs in the preceding code words are maintained, without updatingthe contents of the corresponding mid-term result register.

In the first code word (the first line of the horizontal direction), themid-term result register is initialized because it contains no mid-termresults. When the first detection of an error-containing code in thesector in process is informed by the error-containing code detectionsignal 22, the contents of the corresponding mid-term result registerare not updated, and the subsequent code words are not subjected toerror detection.

Step (e-5): the error corrector 6 receives data read from the buffermemory 4 by means of the error corrector access signal 18 outputted bythe bus control unit 3, corrects an error in the code, and transmits theaccess request signal 17 to the bus control unit 3 to request writing ofthe error-corrected data to the buffer memory 4 again.

Step (e-6): after putting the data bus 11 in commission, the bus controlunit 3 reads the error-corrected data from the error corrector 6 andwrites them to the buffer memory 4. When error correction for one sectoris complete, the error corrector 6 outputs the correction completionsignal 19 to the system control unit 1.

Step (e-7): the system control unit 1 outputs the DMA command 12 to theDMA control unit 2 in order to check to see that the error-correcteddata contain no error in the sector in process, and providesinstructions for data transfer from the buffer memory 4 to the errorcorrector 7. This data transfer involves data from the code wordindicated by the error-containing code word signal 23 outputted togetherwith the error-containing code detection signal 22 outputted first inthe sector in process by the syndrome calculator 5 at step (b-4) up toand including the final code word in the sector. This is within there-calculation range of an EDC shown in FIG. 13, which eliminates theneed for transfer of data in the valid range of the mid-term results ofan EDC in each sector.

Step (e-8): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the error detector 7.

Step (e-9): after putting the data bus 11 in commission, the bus controlunit 3 outputs the buffer memory access signal 14 to the buffer memory 4to read the data therefrom. Then, the bus control unit 3 outputs theerror detector data supply signal 20 to the error detector 7 so as tosupply the data read from the buffer memory 4.

Step (e-10): the error detector 7 executes error detection for thetransferred subsequent data, by using the mid-term results of errordetection stored in the corresponding mid-term result register. Theerror detector 7 then transmits the error detection signal 21 to thesystem control unit 1 so as to inform whether an error has been detectedor not.

Thus, error correction and error detection for one sector is complete.The horizontal error correction for one ECC block is completed byrepeating these steps for 16 sectors.

In Embodiments 1 and 3 having the single mid-term result register 8, there-transfer of data in the case where an error has been detected isstarted from the error-containing code word detected first in one ECCblock. In contrast, in the present embodiment having the 16 mid-termresult registers corresponding to the 16 sectors, it becomes possible tostart the re-transfer of data from the error-containing code worddetected first in each sector. This further reduces the time requiredfor error correction and the power consumption.

The present embodiment has 16 mid-term result registers to be providedto the 16 sectors in one ECC block. Instead, one ECC block can bedivided into regions each composed of several sectors (four, forexample), and the same number of (four) mid-term result registers can beprovided. Thus, while reducing the number of mid-term result registers,the data transfer when an error has been detected can be started fromthe error-containing code word first detected in the divided regions.This reduces the time required for error correction and the powerconsumption in the same manner as in the present embodiment.

Embodiment 6

In the present embodiment, error correction is performed concurrently inthree different ECC blocks by pipeline processing.

FIG. 15 shows the structure of the error correction device 100 of thepresent embodiment. According to the pipeline processing in errorcorrection of the three ECC blocks, horizontal error correction in twoECC blocks and vertical error correction in the other ECC block arecarried out at the same time. To realize the pipeline processing, in theerror correction unit 100 of the present embodiment, the error corrector7 has three mid-term result registers 81, 82, and 83, and the errorcorrector 6 outputs an error correcting position signal 24.

The behavior of the error correction device 100 of the presentembodiment thus structured will be described as follows. While onlyone-time horizontal error correction is performed in Embodiments 1through 5, the present embodiment performs error correction three times:in the horizontal direction, the vertical direction, and the horizontaldirection in this order.

The pipeline processing in the three-time error correction is shown inFIG. 16. At the first stage, horizontal error correction (the first-timeerror correction) is started only for the first ECC block. At the secondstage, vertical error correction (the second-time error correction) isdone for the first ECC block, and horizontal error correction (thefirst-time error correction) is started for the second ECC block. At thethird stage, horizontal error correction (the third-time errorcorrection) is done again for the first ECC block, the vertical errorcorrection (the second-time error correction) is done for the second ECCblock, and horizontal error correction (the first-time error correction)is started for the third ECC block.

In this manner, error correction for as many as three different ECCblocks is performed in parallel at the same stage, and at each stage theerror correction is divided into plural steps. In the case of a DVD, thedirection to read data for EDC calculation is the same as the syndromecalculation in the horizontal direction, and it is possible to performEDC calculation in parallel with the syndrome calculation at thefirst-time and third-time error correction in the horizontal direction.

The flow of the process of the EDC calculation performed concurrentlywith the syndrome calculation at the third stage will be described withreference to FIGS. 15 and 16.

The first-time error correction for the third ECC block will bedescribed as follows. The following steps (f-1) through (f-6) arebasically the same as steps (d-1) through (d-6) in Embodiment 3, so thatthe procedure will not be illustrated.

Step (f-1): in order to execute the first-time error correction for thethird ECC block, the system control unit 1 outputs the DMA command 12 tothe DMA control unit 2 so as to provide instructions to transfer datacorresponding to a horizontal code word in the third ECC block from thebuffer memory 4 to the syndrome calculator 5 and to the error detector7.

Step (f-2): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the syndrome calculator 5 and to the error detector 7.

Step (f-3): the bus control unit 3 puts the data bus 11 in commission,and outputs the buffer memory access signal 14 to the buffer memory 4 toread data therefrom. The bus control unit 3 then outputs the syndromedata supply signal 15 and the error detector data supply signal 20 tothe syndrome calculator 5 and the error detector 7, respectively, so asto supply the data read from the buffer memory 4 to the syndromecalculator 5 and to the error detector 7.

Step (f-4): the syndrome calculator 5 calculates a syndrome 16 of thetransferred horizontal code word, and outputs the syndrome 16 to theerror corrector 6. If the code word contains an error-containing code orif the syndrome is not zero, the syndrome calculator 5 outputs theerror-containing code detection signal 22 to the error detector 7 and tothe system control unit 1. The syndrome calculator 5 also provides thesystem control unit 1 with the error-containing code word signal 23indicating the code word from which an error has been detected in orderto determine the code word to start the syndrome calculation and thevalid range of an EDC in the third-time error correction.

The error detector 7 executes error detection for the transferred datain parallel with the syndrome calculator 5. Prior to the errordetection, the mid-term results of the EDCs in the preceding code wordsstored in the first mid-term result register 81 are reloaded. If thesyndrome is zero when the transfer of the code words is over, themid-term results of the EDCs are stored in the first mid-term resultregister 81 again. When the syndrome is not zero, on the other hand, themid-term results of the EDCs in the previous code words whose syndromeshave been zero are maintained, without updating the contents of thefirst mid-term result register 81. In the first code word (the firstline of the horizontal direction), the first mid-term result register 81is initialized because it contains no mid-term results.

When the detection of the error-containing code is informed by theerror-containing code detection signal 22 as in the first embodiment,the contents of the first mid-term result register 81 are not updated,and the subsequent code words are not subjected to error detection.

Step (f-5): the error corrector 6 corrects an error in the code, andtransmits the access request signal 17 to the bus control unit 3 torequest writing of the error-corrected data to the buffer memory 4.

Step (f-6): after putting the data bus 11 in commission, the bus controlunit 3 reads the error-corrected data from the error corrector 6 andwrites them to the buffer memory 4.

The steps (f-1) through (f-6) are repeated 13 times to complete errorcorrection for one sector, and the error corrector 16 outputs the errorcompletion signal 19 to the system control unit 1.

The above procedure is repeated for 16 sectors to complete thehorizontal error correction of one ECC block. When the syndrome is zeroin all the code words and the results of the EDCs are zero in all thesectors, or when there is no error in one ECC block, error correctioncan be completed only by the first-time error correction.

However, in reality, an error-containing code may exist in some cases.Assume that there is an error-containing code on the fifth line (thefifth code word in the horizontal direction) in the second sector asshown in FIG. 17. In this case, the mid-term results found in the fifthcode word are abandoned, and the contents in the first mid-term resultregister 81 are not updated. As a result, the mid-term results of theEDCs up to and including the fourth code word are held in the firstmid-term result register 81 until the third-time error correction.

The system control unit 1 enters “18”(13+5) indicating the fifth codeword in the second sector as the error-containing code word signal 23and stores it. The error detecting process is suspended on and after thesixth code word in the second sector, and syndrome calculation isexclusively executed.

The second-time error correction of the second ECC block will bedescribed as follows.

When an error is detected, or when the results of the EDC are other thanzero in spite of no error having been detected, the second ECC block issubjected to vertical error correction (the second-time errorcorrection) executed following the horizontal error correction.

Step (f-7): in order to perform the second-time error correction for thesecond ECC block, the system control unit 1 outputs the DMA command 12to the DMA control unit 2, so as to provide instructions to transferdata corresponding to one code word in the vertical direction within thesecond ECC block from the buffer memory 4 only to the syndromecalculator 5. In vertical syndrome calculation, error detection is notexecuted, but the mid-term results of the first-error correction whichare obtained at the second stage and stored in the second mid-termresult register 82 are maintained.

Step (f-8): the DMA control unit 2 outputs the DMA request 13 to the buscontrol unit 3 so as to request the data transfer from the buffer memory4 to the syndrome calculator 5.

Step (f-9): after putting the data bus 11 in commission, the bus controlunit 3 outputs the buffer memory access signal 14 to the buffer memory 4to read the data therefrom. Then, the bus control unit 3 outputs thesyndrome data supply signal 15 to the syndrome calculator 5 so as tosupply the data read from the buffer memory 4.

Step (f-10): the syndrome calculator 5 calculates the syndrome of eachvertical code word in the transferred second ECC block, and outputs thesyndrome 16 to the error corrector 6. The syndrome calculator 5 thenoutputs the error-containing code detection signal 22 to the systemcontrol unit 1 when the code word has an error, or when the syndrome 16is not zero.

Step (f-1): the error corrector 6, after correcting an error in thecode, transmits the access request signal 17 to the bus control unit 3to request writing of the error-corrected data to the buffer memory 4.The error corrector 6 further provides the system control unit 1 withthe error correcting position signal 24 indicating the position of theerror-corrected data. By using the error correcting position signal 24and the error-containing code word signal 23 obtained in the first-timeerror correction, it is determined whether the error correction and theerror detection for one ECC block in the third-time error correctionshould be performed from the beginning or from a halfway point.

Step (f-12): after putting the data bus 11 in commission, the buscontrol unit 3 reads the error-corrected data from the error corrector 6and writes the data to the buffer memory 4.

The vertical error correction for one ECC block is completed byrepeating steps (f-7) through (f-12) as many as the vertical stringsshown in FIG. 2, that is 182 times.

For example, if there is an error-containing code in the sixth line ofthe second sector in the vertical first code word, the system controlunit 1 receives, as the error correcting position signal 24, “19”indicating the position of the code word from the head position in thevertical direction and stores this.

Thus, the horizontal error correction and the vertical error correctionare executed in a similar manner except for the following:

(1) the direction of reading data;

(2) whether or not EDCs are calculated in parallel with syndromes; and

(3) which of the error-containing code word signal and the errorcorrecting position signal is outputted

Finally, the third-time error correction for the first ECC block will bedescribed as follows.

Using the error-containing code word signal 23 found in the first-timeerror correction and the error correcting position signal 24 found inthe second-time error correction, the system control unit 1 determineswhether the error-containing code has been detected and the error hasbeen corrected within the valid range of the mid-term results of theEDCs at the second-time error correction, that is, whether the mid-termresults of the EDCs are valid or not.

The mid-term results of the EDCs obtained in the first-time errorcorrection are valid unless the error correction is done within thevalid range of the mid-term results of the EDCs. In this case, datatransfer is started from the code word on the n-th line indicated by theerror-containing code word signal 23 found in the first-time errorcorrection so as to perform syndrome calculation, and in parallel withthe syndrome calculation, error detection is performed using themid-term results of the EDC held in the third mid-term result register83. On the other hand, when an error in data is corrected within thevalid range of the mid-term results of an EDC, the mid-term results ofthe EDC are invalid, and data transfer is started from the head codeword in the sector from which the error-containing code has beendetected.

Step (f-13): in order to execute the third-time error correction for thethird ECC block, the system control unit 1 outputs the DMA command 12 tothe DMA control unit 2 so as to provide instructions to transfer datacorresponding to a horizontal code word in the third ECC block from thebuffer memory 4 to the syndrome calculator 5 and to the error detector7.

Step (f-14): the DMA control unit 2 outputs the DMA request 13 to thebus control unit 3 so as to request the data transfer from the buffermemory 4 to the syndrome calculator 5 and to the error detector 7.

Step (f-15): the bus control unit 3 puts the data bus 11 in commission,and outputs the buffer memory access signal 14 to the buffer memory 4 toread data therefrom. The bus control unit 3 then outputs the syndromedata supply signal 15 and the error detector data supply signal 20 tothe syndrome calculator 5 and the error detector 7, respectively, so asto supply the data read from the buffer memory 4 to the syndromecalculator 5 and to the error detector 7.

Step (f-16): the syndrome calculator 5 calculates a syndrome 16 of thetransferred horizontal code word, and outputs the syndrome 16 to theerror corrector 6. If the code word contains an error-containing code orif the syndrome is not zero, the syndrome calculator 5 outputs theerror-containing code detection signal 22 to the error detector 7 and tothe system control unit 1. The syndrome calculator 5 also provides thesystem control unit 1 with the error-containing code word signal 23indicating the code word from which an error has been detected.

The error detector 7 executes an error detecting process for thetransferred data in parallel with the syndrome calculator 5. Prior tothe error detection, the mid-term results of the EDCs in the precedingcode words stored in the third mid-term result registers 83 arereloaded. If the syndrome is zero when the transfer of the code words isover, the mid-term results of the EDCs are stored in the third mid-termresult register 83 again. When the syndrome is not zero, on the otherhand, the mid-term results of the EDCs in the preceding code words aremaintained, without updating the contents of the third mid-term resultregister 83. In the first horizontal code word, the third mid-termresult register 83 holds the mid-term results obtained in the first-timeerror correction. If the detection of an error is informed by theerror-containing code detection signal 22, the subsequent code words arenot subjected to error detection.

Step (f-17): the error corrector 6 corrects an error in the code, andtransmits the access request signal 17 to the bus control unit 3 torequest writing of the error-corrected data to the buffer memory 4.

Step (f-18): after putting the data bus 11 in commission, the buscontrol unit 3 reads the error-corrected data from the error corrector 6and writes them to the buffer memory 4.

Step (f-19): the system control unit 1 outputs the DMA command 12 to theDMA control unit 2 in order to check to see that the error-correcteddata contain no error, and provides instructions for data transfer fromthe buffer memory 4 to the error detector 7. This data transfer involvesdata from the code word indicated by the error-containing code wordsignal 23 outputted together with the error-containing code detectionsignal 22 outputted first by the syndrome calculator 5 at step (f-4).

Step (f-20): the DMA control unit 2 outputs the DMA request 13 to thebus control unit 3 so as to request the data transfer from the buffermemory 4 to the error detector 7.

Step (f-21): after putting the data bus 11 in commission, the buscontrol unit 3 outputs the buffer memory access signal 14 to the buffermemory 4 to read the data therefrom. Then, the bus control unit 3outputs the error detector data supply signal 20 to the error detector 7so as to supply the data read from the buffer memory 4.

Step (f-22): using the mid-term results of the error detection stored inthe third mid-term register 83, the error detector 7 executes errordetection of the transferred subsequent data, and transmits the errordetection signal 21 to the system control unit 1 so as to inform whetheran error has been detected or not.

The error correction for one sector is completed by repeating steps(f-13) through (f-22) 13 times, and the horizontal error correction forone ECC block is completed by repeating this procedure for 16 sectors.In the third-time error correction, if the mid-term results of errordetection obtained in the first-time error correction and stored in thethird mid-term register 83 are valid, the number of repetition can belessened in accordance with the position of the code word from which theerror-containing code has been detected in the first-time errorcorrection. This is the advantage of the present embodiment.

For example, in the second-time error correction shown in FIG. 17, whenerror-containing codes are all contained in or after the sixth line ofthe second sector, the mid-term results of the EDCs held in the mid-termresult register 81 are valid. With the use of the mid-term results, datatransfer is started from the sixth code word in the second sector so asto perform syndrome calculation and error detection.

However, when an error-containing code is contained before the fifthline of the second sector, namely, in the second line of the secondsector, the mid-term results of the EDCs become invalid. In this case,data transfer is started from the head of the second sector that is thesector following the sector (the first sector in this case) in whichthere is no error to be corrected in the second-time error correction.

Since the EDC calculation is performed one sector at a time, the startof data transfer is restricted to the head of a sector, using theerror-containing code word signal and the error correcting positionsignal as data indicating the sector having an error-containing code.This can reduce the number of registers to hold the first-time mid-termresults although more amount of data must be transferred for correctionagain than in the case where the start of the data transfer is indicatedin code word units.

Finally, steps (f-19) through (f-22) are executed once so as toterminate the error detection of one ECC block. In this case, the datatransfer from the buffer memory 14 to the error detector 7 is startedfrom the code word indicated by the error-containing code word signal 23first outputted from the syndrome calculator 5 in the third-time errorcorrection.

This effect shown in Embodiments 1 through 3 is also provided by thepresent embodiment.

As described hereinbefore, in the present embodiment, three-time errorcorrection with the single error corrector 6 is performed bytransferring data to the error detector 7 at the same time as the datatransfer from the buffer memory 4 to the syndrome calculator 5. Until anerror-containing code is detected by the syndrome calculator 5, errordetection is executed in parallel with the syndrome calculation. In theerror detection after the error corrector 6 has corrected an error, themid-term results of error detection obtained before the detection of theerror-containing code are used. This eliminates the need for all data inone ECC block being transferred from the buffer memory 4 to the errordetector 7, thereby enabling an error detecting process to be startedfrom a halfway point. This greatly reduces the time required for errorcorrection and the power consumption in the same manner as in thepresent embodiment.

Although the present embodiment describes three-time error correction,it can be more than three times. It goes without saying that withprobable technological development in the future, five-time errorcorrection for a DVD could be realized by providing five mid-term resultregisters, and that the process of EDCs could be greatly reduced inaccordance with the degree of errors.

When there are only few errors in the second-time error correction, thethird-time error correction can be canceled and only error detection canbe executed.

In the pipeline processing shown in FIG. 16 of the present embodiment,in order to improve throughput, data are stored in the buffer memory 4in descending order of ECC blocks, and after the error correction, dataare transferred downstream in descending order in unit time of thepipeline processing. Instead, some ECC blocks could be storedcollectively in the buffer memory 4 (so-called batch processing) andafter the error correction, some ECC blocks could be transferreddownstream collectively in the descending order. This system isconvenient for the case where access to the data-storing medium is oftenbusy.

The system is also convenient when discrete scenes are reproduced athigh speed in accordance with the predetermined procedure in order toretrieve specific images in a movie. In this case, it is necessary toprovide a means compliant with the standard so as to recognize eachscene and discrete scenes.

The system will be also convenient in the case where error correction isneeded across several ECC blocks because a disk has a blemish or a stainwhile being handled by users, although probable technologicaldevelopment in the future will lessen error correction. Thus, most ECCblocks with few error correction would be flown downstream as they are,and ECC blocks requiring minor error correction are collectivelysubjected to error correction, and when error correction is difficult,another process would be applied to collective ECC blocks.

Embodiment 7

While in Embodiment 6 , error correction and error detection areperformed in the first-time error correction for a code word temporarilystored in the buffer memory 4, in the present embodiment the first-timeerror correction and detection are performed in parallel withdemodulation. In order to realize this feature, as shown in FIG. 18, theerror detection device of the present embodiment comprises two syndromecalculators and two error detectors. The error detection device will bedescribed as follows with reference to FIG. 18.

The drawing includes the first and second syndrome calculators 51 and52, and the first and second error detectors 71 and 72. The upstream anddownstream units are not illustrated.

The error detection device 100 receives data stored in an optical diskas a reception code 29 from the amplifier. The reception code 29 isentered to the demodulator 10. The demodulated code is stored in thebuffer memory 4 by means of the demodulating code input signal 25outputted from the bus control unit 3, and also supplied to the secondsyndrome calculator 52 and to the second error detector 72.

In order to perform error correction and error detection with the codeword read from the buffer memory 4, the first syndrome calculator 51 andthe first error detector 71 are arranged separately. The input of theerror corrector 6 is connected to a selection circuit 60 so that theerror corrector 6 can select between the syndromes transmitted from thefirst and second syndrome calculators 51 and 52.

The second syndrome calculator 52 calculates a syndrome 162 of eachtransferred horizontal code word, and outputs the syndrome 162 to theerror corrector 6. If the code word contains an error-containing code orif the syndrome 162 is not zero, the second syndrome calculator 52outputs the error-containing code detection signal 222 to the seconderror corrector 72 and to the system control unit 1. The second syndromecalculator 52 also provides the system control unit 1 with anerror-containing code word signal 232 indicating the code word fromwhich an error has been detected.

The second error detector 72 executes an error detecting calculation forthe transferred data in parallel with this.

When the second syndrome calculator 52 detects an error-containing codeword, the error corrector 6 performs error correction, and the resultsare written in the buffer memory 4. Then, vertical error detection andcorrection and the second-time and later horizontal error detection andcorrection are executed by the first syndrome calculator 51 and thefirst error detector 71. Prior to the error detection, the mid-termresults of the EDCs in the preceding code words stored in the mid-termresult register assigned in the pipeline processing are reloaded. If thesyndrome is zero when the transfer of the code words is over, themid-term results of the EDCs are stored in the mid-term result registeragain. When the syndrome is not zero, on the other hand, the mid-termresults of the EDCs in the preceding code words are maintained, withoutupdating the contents of the mid-term result register.

FIG. 19 conceptually shows changes in the contents (structure, flow) ofthe pipeline processing due to the provision of the second syndromecalculator 52, or how the process is speeded up. This drawing indicatesthat the process is speeded up by one step.

Embodiment 8

The present embodiment is an improvement of Embodiment 7.

In Embodiment 7 the second syndrome calculator 52 and the second errordetector 72 process demodulated data only. In this case, while thesecond syndrome calculator 52 is performing syndrome calculation fordemodulated data (a code word) one time, the first syndrome calculator51 executes syndrome calculation for data in the buffer memory 4 twice.Thus, if these syndrome calculators have an equal capacity, the secondsyndrome calculator 52 will stand idle for some time.

CPU-related data require highly precise error correction, and datastored in media that have been under poor storage conditions for a longtime period may demand repeated error correction. It is highly likely insuch a case that if the first syndrome calculator 51 exclusivelyprocesses data in the buffer memory 4, the second syndrome calculator 52sits idle. Hence, in the present embodiment, after the demodulated dataare stored in the buffer memory 4, the second syndrome calculator 52 isalso designed to perform error correction.

FIG. 20 shows the structure of the main part of the error correctiondevice of the present embodiment.

The error correction device of the present embodiment basically has thesame structure as the device of Embodiment 7 shown in FIG. 18 exceptthat the first and second syndrome calculators 51, 52 and the first andsecond error detectors 71, 72 are connected also to the buffer memory 4and that selectors 301, 302 select between data immediately afterdemodulation and data in the buffer memory 4 as a target of process.

The control unit 300 controls the ECC block, the sector, the sectorgroup in process, the number of strings, and the number of times ofcorrection for each component unit (means) of the device by formingreference lists. Based on the reference lists, the control unit 300further controls the storage of the mid-term results of error correctionto an appropriate address in the mid-term result register 80, andswitching operations. FIGS. 21A and 21B conceptually show the contentsof the reference table 303. FIG. 21A is a reference list containing ECCblocks and selectors which are being processed in each component unit.FIG. 21B is a reference list containing the position of data which arebeing processed in each ECC block and the number of times of errorcorrection.

The control unit 300 refers to these lists synchronously with clocksignals, and updates the contents of these lists to make each componentunit perform a necessary process. With the present invention, it is notso difficult to compose, refer, and update these lists in terms ofhardware or software, so that the description of the specific contentswill be omitted.

As described hereinbefore, according to the present embodiment, databefore the syndrome calculators 51, 52 detect an error-containing codecan be subjected to an error detecting process in parallel with syndromecalculation, which eliminates the need for all data to be transferredfrom the buffer memory 4 to the first and second error correctors 71, 72after error correction. This can reduce the time required for a sequenceof error correcting process.

Pipeline processing for a plurality of ECC blocks can reduce the timerequired for a sequence of error correcting process.

Performing syndrome calculation and error detection with the writing ofdemodulated data to the buffer memory 4 can reduce the time required fora sequence of error correcting process.

Some types of data allow the writing of subsequent data to the buffermemory 4 and the transfer of error-corrected data downstream to beperformed at the same time, which reduces the time required for asequence of error correcting process.

The error correction is done in accordance with the contents andconditions of data, which reduces the time required for a sequence oferror correcting process.

A combination of these processes can further reduce the time requiredfor a sequence of error correcting process.

The present invention, which has been described based on theembodiments, is not restricted to them, and can be structured asfollows.

1) Error-containing data on the buffer memory are temporarily read intothe error corrector, and the error-corrected data are written back intothe buffer memory. Instead of this, the address of the data on thebuffer memory can be exclusively transmitted from the error corrector tothe bus control unit, and the error in the data read based on theaddress from the buffer memory can be corrected in the bus control unitand written back to the buffer memory.

2) In the inventions of aspects 2, 4, and 6, instead of the systemcontrol unit controlling transfer data, the syndrome calculator can beprovided with a detecting means for detecting from which code word anerror-containing code has been detected, so the detection means caninform the system control unit of the code word detected. As a result,data can be transferred to the syndrome calculator by making the DMAcontrol unit and the syndrome calculator do the handshake every codeword. Then, the syndrome calculator informs only the presence or absenceof a detected error to the DMA control unit. Therefore, data transfer iscontrolled within the DMA control unit.

The DMA transfer may be adopted in the inventions of the other aspects.

3) The number of bits in main data and in parity of a DVD can bedifferent, depending on various standards. In some cases, the verticaldirection and the horizontal direction can be opposite, or the order oferror detection can be opposite (provided that it is substantially thesame as the present invention).

4) In the invention of aspect 11 and the like, the number of sectorgroups can be varied between the portion where an error is highly likelyto arise, and the other portion, due to the difference in position on aDVD such as an end portion and the center, and the fabrication method.

5) The error detector may not perform error detection although data aretransferred to the error detector after the syndrome detection done bythe syndrome calculator so as to exert substantially the same actionsand effects as the present invention.

6) In the pipeline processing, the number of repetition of errorcorrection for ECC blocks to be processed can be changed depending onthe type of data and experience.

7) The number of times of error correction can be changed depending onthe use pattern of data by the users. To be more specific, the numbercan be reduced when images are reproduced at high speed for retrieval.In this case, switching operations of the users are detected on themachine side, and processes are performed accordingly. To realize this,necessary circuits and programs are provided at the fabricating stage.

8) In the eighth embodiment, the first and second syndrome calculatorsperform syndrome calculation for demodulated code words. Instead, one ofthe syndrome calculators can do it.

9) In the seventh embodiment, the syndrome calculator for demodulatedcode words can be slower in process and less expensive than the othersyndrome calculator.

10) The error correction can be applied to broadcast such as a FMmultiplex broadcast.

1-6. (canceled)
 7. An error correction device comprising; a buffermemory for storing at least one ECC block of data having a structurewhere a plurality of error correcting code words each comprising a dataunit and a parity unit are arranged in vertical direction and horizontaldirection so as to repeat error correction a plurality of number oftimes, and where predetermined data composed of a predetermined numberof code words in the vertical direction or the horizontal direction(data in the horizontal direction are referred to as sector) as a unitare subjected to error correction; a syndrome calculating means forgenerating syndrome for data read from said buffer memory; an errorcorrecting means for correcting error-containing data in said buffermemory by detecting an error position from the syndrome generated bysaid syndrome calculating means and by calculating an error value; anerror detecting means for detecting an error in error-corrected datagenerated by said error correcting means; a bus control means forcontrolling data transfer between said buffer memory, said syndromecalculating means, said error correcting means, and said error detectingmeans; and a system control means for performing various processes forerror correction in predetermined procedures a necessary number oftimes, wherein said system control means comprises: a first-time errorcorrection sub means for reading data from said buffer memory in a samedirection as calculation for an error detecting code as a first-timeerror correction; for transferring the read data to said syndromecalculating means and to said error detecting means concurrently untilsaid syndrome calculating means detects an error-containing code; formaking said syndrome calculating means execute syndrome calculation andsaid error detecting means execute error detection in parallel; formaking said error correcting means execute error correction when saidsyndrome calculating means has detected an error-containing code; andfor making one of said syndrome calculating means and said errorcorrecting means provide the system control means with information whichdesignates a code word containing the error-containing code; aneven-numbered error correction sub means for reading a code word in adifferent direction from a preceding odd-numbered error correction; fortransferring the code word to said syndrome calculating means and tosaid error detecting means concurrently until said syndrome calculatingmeans detects an error-containing code; for making said syndromecalculating means execute syndrome calculation and said error detectingmeans execute error detection in parallel; for making said errorcorrecting means execute error correction when said syndrome calculatingmeans detects an error-containing code; and for making said errorcorrecting means provide said system control means with informationwhich designates the position of the error-containing code in an errorcorrecting code word obtained in the error correction; a non-error rangedesignating sub means for designating, one sector at a time, a rangefrom which an error-containing code has not been detected at theodd-numbered error correction or the subsequent even-numbered errorcorrection, based on said information that designates the code wordincluding the error-containing code and said information that designatesthe position of the error-containing code in the error correcting codeword; an odd-numbered error correction sub means for, as an odd-numberederror correction as a third-time or later error correction, providingconcurrently said syndrome calculating means and said error detectingmeans with a code in the same direction as in the previous odd-numberederror correction except for a sector in one ECC block which has beendesignated by said non-error range designating sub means as the rangefrom which an error-containing code has not been detected in and beforethe preceding even-numbered error correction until said syndromecalculating means detects an error-containing code; for making saidsyndrome calculating means execute syndrome calculation and said errordetecting means execute error detection in parallel; for making saiderror correcting means execute error correction when said syndromecalculating means detects an error-containing code; and for making oneof said syndrome calculating means and said error correcting meansprovide said system control means with information which designates thecode word including the error-containing code; and a number-of-timescontrol sub means for repeating the odd-numbered error correction andthe even-numbered error correction a predetermined number of times. 8.The error correction device of claim 7, wherein said number-of-timescontrol sub means is a three-time repetition control sub means forrepeating the error correction three times at most.
 9. The errorcorrection device of claim 7 further comprising a storing means forstoring mid-term results, in code word units, of each code word fromwhich no error has been detected in the error detecting process done bysaid error detecting means until said syndrome calculating means detectsan error-containing code, wherein said non-error range designating submeans is a non-error sector code word range designating sub means fordesignating, in code word units of a sector, a range from which anerror-containing code has not been detected in the odd-numbered errorcorrection or the subsequent even-numbered error correction, based onsaid information that designates the code word including theerror-containing code and on said information that designates theposition of the error-containing code in the error correcting code word;and said odd-numbered error correction sub means is an odd-numberederror correction sub means with mid-term results for, in the third-timeor later odd-numbered error correction, making said bus control meansstart a concurrent data transfer not at the head but at the code word ofthe sector from which an error-containing code has been detected, basedon the information designated by said non-error sector code word rangedesignating sub means; for making said syndrome calculating means startsyndrome calculation at the code word; and for making said errordetecting means start error detection at a code word somewhere in themiddle of the sector by using contents stored in said storing means asan initial value.
 10. The error correction device of claim 7 furthercomprising a sector-basis storing means for storing mid-term results, ona sector-by-sector basis, in code word units, of each code word fromwhich no error has been detected in the error detecting process done bysaid error detecting means, until said syndrome calculating meansdetects an error-containing code, wherein said non-error rangedesignating sub means is a sector-basis non-error code word rangedesignating sub means for designating, on a sector-by-sector basis, incode word units, a range from which an error-containing code has notbeen detected in the odd-numbered error correction or the subsequenteven-numbered error correction, based on said information thatdesignates the code word including the error-containing code and on saidinformation that designates the position of the error-containing code inthe error correcting code word; and said odd-numbered error correctionsub means is an odd-numbered error correction sub means with mid-termresults for, in the third-time or later odd-numbered error correction,making said bus control means start a concurrent data transfer not atthe head but at the code word of each sector from which anerror-containing code has been detected, based on the informationdesignated by said sector-basis non-error code word range designatingsub means; for making said syndrome calculating means start syndromecalculation at the code word; and for making said error detecting meansstart error detection at a code word somewhere in the middle of thesector by using contents stored in said sector-basis storing means as aninitial value.
 11. The error correction device of claim 7 furthercomprising a sector-group-basis storing means for storing mid-termresults, on a sector-group-by-sector-group-basis, in code word units, ofeach code word from which no error has been detected in the errordetecting process done by said error detecting means until said syndromecalculating means detects an error-containing code, wherein saidnon-error range designating sub means is a sector-group-basis non-errorcode word range designating sub means for designating, on asector-group-by-sector-group-basis, in code word units, a range fromwhich an error-containing code has not been detected in the odd-numberederror correction or the subsequent even-numbered error correction, basedon said information that designates the code word including theerror-containing code and on said information that designates theposition of the error-containing code in the error correcting code word;and said odd-numbered error correction sub means is an odd-numberederror correction sub means with mid-term results for, in the third-timeor later odd-numbered error correction, making said bus control meansstart a concurrent data transfer not at the head but at the code word ofeach sector group from which an error-containing code has been detected,based on the information designated by said sector-group-basis non-errorcode word range designating sub means; for making said syndromecalculating means start syndrome calculation at the code word; and formaking said error detecting means start error detection at a code wordsomewhere in the middle of the sector by using contents stored in saidsector-group-basis storing means as an initial value.
 12. The errorcorrection device of claim 7, wherein error correction is performed inparallel for data in a plurality of ECC blocks each having a structurewhere a plurality of error correcting code words each comprising a dataunit and a parity unit are arranged in vertical direction and horizontaldirection so as to repeat error correction a plurality of number oftimes, and where predetermined data composed of a predetermined numberof code words in the vertical direction or the horizontal direction(data in the horizontal direction are referred to as sector) as a unitare subjected to the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said plural-ECC-block-division buffer memory; and formaking the storage known to said bus control means, said syndromecalculating means, said error detecting means, and said error correctingmeans; a means-basis ECC block recognition sub means for recognizing adata transfer from said bus control means to said syndrome calculatingmeans, to said error detecting means, and to said error correcting meansfor error detection and error correction; for recognizing the errorcorrection done by said error correcting means; for recognizing writingof error-corrected data to said plural-ECC-block-division buffer memorydone by said bus control means; for recognizing an ECC block in processwhen said error detecting means stores mid-term results to saidplural-ECC-block-division storing means, and for selecting ECC blocks tobe processed; and an ECC block notification sub means in sub means-basispipeline processing for notifying said first error detecting sub means,said even-numbered error correction sub means, said odd-numbered errorcorrection sub means, said number-of-times control sub means, and saidDMA transfer instruction sub means contained in said system controlmeans that the error-corrected ECC blocks have been transmitteddownstream and new ECC blocks to be processed have been stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 13. The error correction device of claim9, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said plural-ECC-block-division buffer memory; and formaking the storage known to said bus control means, said syndromecalculating means, said error detecting means, and said error correctingmeans; a means-basis ECC block recognition sub means for recognizing adata transfer from said bus control means to said syndrome calculatingmeans, to said error detecting means, and to said error correcting meansfor error detection and error correction; for recognizing the errorcorrection done by said error correcting means; for recognizing writingof error-corrected data to said plural-ECC-block-division buffer memorydone by said bus control means; for recognizing an ECC block in processwhen said error detecting means stores mid-term results to saidplural-ECC-block-division storing means, and for selecting ECC blocks tobe processed; and an ECC block notification sub means in sub means-basispipeline processing for notifying said first error detecting sub means,said even-numbered error correction sub means, said odd-numbered errorcorrection sub means, said number-of-times control sub means, and saidDMA transfer instruction sub means contained in said system controlmeans that the error-corrected ECC blocks have been transmitteddownstream and new ECC blocks to be processed have been stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 14. The error correction device of claim10, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said plural-ECC-block-division buffer memory; and formaking the storage known to said bus control means, said syndromecalculating means, said error detecting means, and said error correctingmeans; a means-basis ECC block recognition sub means for recognizing adata transfer from said bus control means to said syndrome calculatingmeans, to said error detecting means, and to said error correcting meansfor error detection and error correction; for recognizing the errorcorrection done by said error correcting means; for recognizing writingof error-corrected data to said plural-ECC-block-division buffer memorydone by said bus control means; for recognizing an ECC block in processwhen said error detecting means stores mid-term results to saidplural-ECC-block-division storing means, and for selecting ECC blocks tobe processed; and an ECC block notification sub means in sub means-basispipeline processing for notifying said first error detecting sub means,said even-numbered error correction sub means, said odd-numbered errorcorrection sub means, said number-of-times control sub means, and saidDMA transfer instruction sub means contained in said system controlmeans that the error-corrected ECC blocks have been transmitteddownstream and new ECC blocks to be processed have been stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 15. The error correction device of claim11, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said plural-ECC-block-division buffer memory; and formaking the storage known to said bus control means, said syndromecalculating means, said error detecting means, and said error correctingmeans; a means-basis ECC block recognition sub means for recognizing adata transfer from said bus control means to said syndrome calculatingmeans, to said error detecting means, and to said error correcting meansfor error detection and error correction; for recognizing the errorcorrection done by said error correcting means; for recognizing writingof error-corrected data to said plural-ECC-block-division buffer memorydone by said bus control means; for recognizing an ECC block in processwhen said error detecting means stores mid-term results to saidplural-ECC-block-division storing means, and for selecting ECC blocks tobe processed; and an ECC block notification sub means in sub means-basispipeline processing for notifying said first error detecting sub means,said even-numbered error correction sub means, said odd-numbered errorcorrection sub means, said number-of-times control sub means, and saidDMA transfer instruction sub means contained in said system controlmeans that the error-corrected ECC blocks have been transmitteddownstream and new ECC blocks to be processed have been stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 16. The error correction device of claim7, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction; said buffer memory is an ECC-block-basis buffermemory for storing, on a block-by-block basis, ECC blocks to beprocessed in parallel; said storing means for storing mid-term resultsof an error detecting process generated by said error detecting means isan ECC-block-and-code word-division storing means for storing ECC blocksin process on a block-by-block basis, and code words in each ECC block,in each sector, or in each sector group, on a string-by-string basis;said system control means comprises: a means-basis ECC block pipelineprocessing notification sub means for transmitting ECC blocks which havebeen subjected to error correction downstream; for storing ECC blocks tobe processed next to said ECC-block-basis buffer memory; and for makingthe storage known to said bus control means, said syndrome calculatingmeans, said error detecting means, and said error correcting means; ameans-basis ECC block code word recognition sub means for selecting codewords of the ECC blocks to be processed, in accordance with the contentsstored in said ECC-block-and-code word-division storing means, incontrolling a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; incontrolling the error correction done by said error correcting means; incontrolling writing of error-corrected data to said ECC-block-basisbuffer memory done by said bus control means; in storing mid-termresults to said ECC-block-and-code word-division storing means by saiderror detecting means; and an ECC block code word recognition sub meansin sub means-basis pipeline processing for making said first errordetecting sub means, said even-numbered error correction sub means, saideven-numbered error correction sub means, said number-of-times controlsub means, and said DMA transfer instruction sub means in said systemcontrol means recognize that the error-corrected ECC blocks have beentransmitted downstream and new ECC blocks to be processed have beenstored in said ECC-block-basis buffer memory, and further making thesesame sub means contained in said system control means recognize the ECCblocks and the code words which are to be processed therein.
 17. Theerror correction device of claim 9, wherein error correction isperformed in parallel for data in a plurality of ECC blocks each havinga structure where a plurality of error correcting code words eachcomprising a data unit and a parity unit are arranged in verticaldirection and horizontal direction so as to repeat error correction aplurality of number of times, and where predetermined data composed of apredetermined number of code words in the vertical direction or thehorizontal direction (data in the horizontal direction are referred toas sector) as a unit are subjected to the error correction; said buffermemory is an ECC-block-basis buffer memory for storing, on ablock-by-block basis, ECC blocks to be processed in parallel; saidstoring means for storing mid-term results of an error detecting processgenerated by said error detecting means is an ECC-block-and-codeword-division storing means for storing ECC blocks in process on ablock-by-block basis, and code words in each ECC block, in each sector,or in each sector group, on a string-by-string basis; said systemcontrol means comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said ECC-block-basis buffer memory; and for making thestorage known to said bus control means, said syndrome calculatingmeans, said error detecting means, and said error correcting means; ameans-basis ECC block code word recognition sub means for selecting codewords of the ECC blocks to be processed, in accordance with the contentsstored in said ECC-block-and-code word-division storing means, incontrolling a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; incontrolling the error correction done by said error correcting means; incontrolling writing of error-corrected data to said ECC-block-basisbuffer memory done by said bus control means; in storing mid-termresults to said ECC-block-and-code word-division storing means by saiderror detecting means; and an ECC block code word recognition sub meansin sub means-basis pipeline processing for making said first errordetecting sub means, said even-numbered error correction sub means, saideven-numbered error correction sub means, said number-of-times controlsub means, and said DMA transfer instruction sub means in said systemcontrol means recognize that the error-corrected ECC blocks have beentransmitted downstream and new ECC blocks to be processed have beenstored in said ECC-block-basis buffer memory, and further making thesesame sub means contained in said system control means recognize the ECCblocks and the code words which are to be processed therein.
 18. Theerror correction device of claim 10, wherein error correction isperformed in parallel for data in a plurality of ECC blocks each havinga structure where a plurality of error correcting code words eachcomprising a data unit and a parity unit are arranged in verticaldirection and horizontal direction so as to repeat error correction aplurality of number of times, and where predetermined data composed of apredetermined number of code words in the vertical direction or thehorizontal direction (data in the horizontal direction are referred toas sector) as a unit are subjected to the error correction; said buffermemory is an ECC-block-basis buffer memory for storing, on ablock-by-block basis, ECC blocks to be processed in parallel; saidstoring means for storing mid-term results of an error detecting processgenerated by said error detecting means is an ECC-block-and-codeword-division storing means for storing ECC blocks in process on ablock-by-block basis, and code words in each ECC block, in each sector,or in each sector group, on a string-by-string basis; said systemcontrol means comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said ECC-block-basis buffer memory; and for making thestorage known to said bus control means, said syndrome calculatingmeans, said error detecting means, and said error correcting means; ameans-basis ECC block code word recognition sub means for selecting codewords of the ECC blocks to be processed, in accordance with the contentsstored in said ECC-block-and-code word-division storing means, incontrolling a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; incontrolling the error correction done by said error correcting means; incontrolling writing of error-corrected data to said ECC-block-basisbuffer memory done by said bus control means; in storing mid-termresults to said ECC-block-and-code word-division storing means by saiderror detecting means; and an ECC block code word recognition sub meansin sub means-basis pipeline processing for making said first errordetecting sub means, said even-numbered error correction sub means, saideven-numbered error correction sub means, said number-of-times controlsub means, and said DMA transfer instruction sub means in said systemcontrol means recognize that the error-corrected ECC blocks have beentransmitted downstream and new ECC blocks to be processed have beenstored in said ECC-block-basis buffer memory, and further making thesesame sub means contained in said system control means recognize the ECCblocks and the code words which are to be processed therein.
 19. Theerror correction device of claim 11, wherein error correction isperformed in parallel for data in a plurality of ECC blocks each havinga structure where a plurality of error correcting code words eachcomprising a data unit and a parity unit are arranged in verticaldirection and horizontal direction so as to repeat error correction aplurality of number of times, and where predetermined data composed of apredetermined number of code words in the vertical direction or thehorizontal direction (data in the horizontal direction are referred toas sector) as a unit are subjected to the error correction; said buffermemory is an ECC-block-basis buffer memory for storing, on ablock-by-block basis, ECC blocks to be processed in parallel; saidstoring means for storing mid-term results of an error detecting processgenerated by said error detecting means is an ECC-block-and-codeword-division storing means for storing ECC blocks in process on ablock-by-block basis, and code words in each ECC block, in each sector,or in each sector group, on a string-by-string basis; said systemcontrol means comprises: a means-basis ECC block pipeline processingnotification sub means for transmitting ECC blocks which have beensubjected to error correction downstream; for storing ECC blocks to beprocessed next to said ECC-block-basis buffer memory; and for making thestorage known to said bus control means, said syndrome calculatingmeans, said error detecting means, and said error correcting means; ameans-basis ECC block code word recognition sub means for selecting codewords of the ECC blocks to be processed, in accordance with the contentsstored in said ECC-block-and-code word-division storing means, incontrolling a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; incontrolling the error correction done by said error correcting means; incontrolling writing of error-corrected data to said ECC-block-basisbuffer memory done by said bus control means; in storing mid-termresults to said ECC-block-and-code word-division storing means by saiderror detecting means; an ECC block code word recognition sub means insub means-basis pipeline processing for making said first errordetecting sub means, said even-numbered error correction sub means, saideven-numbered error correction sub means, said number-of-times controlsub means, and said DMA transfer instruction sub means in said systemcontrol means recognize that the error-corrected ECC blocks have beentransmitted downstream and new ECC blocks to be processed have beenstored in said ECC-block-basis buffer memory, and further making thesesame sub means contained in said system control means recognize the ECCblocks and the code words which are to be processed therein.
 20. Theerror correction device of claim 7, wherein error correction isperformed in parallel for data in a plurality of ECC blocks each havinga structure where a plurality of error correcting code words eachcomprising a data unit and a parity unit are arranged in verticaldirection and horizontal direction so as to repeat error correction aplurality of number of times, and where predetermined data composed of apredetermined number of code words in the vertical direction or thehorizontal direction (data in the horizontal direction are referred toas sector) as a unit are subjected to the error correction, wherein saidbuffer memory is a plural-ECC-block-division buffer memory correspondingto a plurality of ECC blocks to be processed in parallel; said storingmeans for storing mid-term results of an error detecting processgenerated by said error detecting means is an ECC-block-division storingmeans for storing said plurality of ECC blocks on a block-by-blockbasis; said system control means comprises: a collective-typemeans-basis ECC block pipeline processing notification sub means forcollectively transmitting ECC blocks which have been subjected to errorcorrection downstream; for collectively storing ECC blocks to beprocessed next to said plural-ECC-block-division buffer memory; and formaking the storage known to said bus control means, said syndromecalculating means, said error detecting means, and said error correctingmeans; a collective-type means-basis ECC block recognition sub means forrecognizing a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; forrecognizing the error correction done by said error correcting means;for recognizing writing of error-corrected data to saidplural-ECC-block-division buffer memory by said bus control means; forrecognizing ECC blocks in process when said error detecting means storesmid-term results to said plural-ECC-block-division storing means, andfor selecting ECC blocks to be processed; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 21. The error correction device of claim 9wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a collective-type means-basis ECC block pipelineprocessing notification sub means for collectively transmitting ECCblocks which have been subjected to error correction downstream; forcollectively storing ECC blocks to be processed next to saidplural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block recognition sub means forrecognizing a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; forrecognizing the error correction done by said error correcting means;for recognizing writing of error-corrected data to saidplural-ECC-block-division buffer memory by said bus control means; forrecognizing ECC blocks in process when said error detecting means storesmid-term results to said plural-ECC-block-division storing means, andfor selecting ECC blocks to be processed; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 22. The error correction device of claim10, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a collective-type means-basis ECC block pipelineprocessing notification sub means for collectively transmitting ECCblocks which have been subjected to error correction downstream; forcollectively storing ECC blocks to be processed next to saidplural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block recognition sub means forrecognizing a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; forrecognizing the error correction done by said error correcting means;for recognizing writing of error-corrected data to saidplural-ECC-block-division buffer memory by said bus control means; forrecognizing ECC blocks in process when said error detecting means storesmid-term results to said plural-ECC-block-division storing means, andfor selecting ECC blocks to be processed; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 23. The error correction device of claim11, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction, wherein said buffer memory is aplural-ECC-block-division buffer memory corresponding to a plurality ofECC blocks to be processed in parallel; said storing means for storingmid-term results of an error detecting process generated by said errordetecting means is an ECC-block-division storing means for storing saidplurality of ECC blocks on a block-by-block basis; said system controlmeans comprises: a collective-type means-basis ECC block pipelineprocessing notification sub means for collectively transmitting ECCblocks which have been subjected to error correction downstream; forcollectively storing ECC blocks to be processed next to saidplural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block recognition sub means forrecognizing a data transfer from said bus control means to said syndromecalculating means, to said error detecting means, and to said errorcorrecting means for error detection and error correction; forrecognizing the error correction done by said error correcting means;for recognizing writing of error-corrected data to saidplural-ECC-block-division buffer memory by said bus control means; forrecognizing ECC blocks in process when said error detecting means storesmid-term results to said plural-ECC-block-division storing means, andfor selecting ECC blocks to be processed; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 24. The error correction device of claim7, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction; said buffer memory is an ECC-block-basis buffermemory for storing, on a block-by-block basis, ECC blocks to beprocessed in parallel; said storing means for storing mid-term resultsof an error detecting process generated by said error detecting means isan ECC-block-and-code word-division storing means for storing ECC blocksin process on a block-by-block basis, and code words in each ECC block,in each sector, or in each sector group, on a string-by-string basis;said system control means comprises: a collective-type means-basis ECCblock pipeline processing notification sub means for collectivelytransmitting ECC blocks which have been subjected to error correctiondownstream; for collectively storing ECC blocks to be processed next tosaid plural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block code word recognition sub meansfor selecting code words of the ECC blocks to be processed, inaccordance with the contents stored in said ECC-block-and-codeword-division storing means, in controlling a data transfer from saidbus control means to said syndrome calculating means, to said errordetecting means, and to said error correcting means for error detectionand error correction; in controlling the error correction done by saiderror correcting means; in controlling writing of error-corrected datato said ECC-block-basis buffer memory done by said bus control means; instoring mid-term results to said ECC-block-and-code word-divisionstoring means by said error detecting means; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 25. The error correction device of claim9, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction; said buffer memory is an ECC-block-basis buffermemory for storing, on a block-by-block basis, ECC blocks to beprocessed in parallel; said storing means for storing mid-term resultsof an error detecting process generated by said error detecting means isan ECC-block-and-code word-division storing means for storing ECC blocksin process on a block-by-block basis, and code words in each ECC block,in each sector, or in each sector group, on a string-by-string basis;said system control means comprises: a collective-type means-basis ECCblock pipeline processing notification sub means for collectivelytransmitting ECC blocks which have been subjected to error correctiondownstream; for collectively storing ECC blocks to be processed next tosaid plural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block code word recognition sub meansfor selecting code words of the ECC blocks to be processed, inaccordance with the contents stored in said ECC-block-and-codeword-division storing means, in controlling a data transfer from saidbus control means to said syndrome calculating means, to said errordetecting means, and to said error correcting means for error detectionand error correction; in controlling the error correction done by saiderror correcting means; in controlling writing of error-corrected datato said ECC-block-basis buffer memory done by said bus control means; instoring mid-term results to said ECC-block-and-code word-divisionstoring means by said error detecting means; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 26. The error correction device of claim10, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction; said buffer memory is an ECC-block-basis buffermemory for storing, on a block-by-block basis, ECC blocks to beprocessed in parallel; said storing means for storing mid-term resultsof an error detecting process generated by said error detecting means isan ECC-block-and-code word-division storing means for storing ECC blocksin process on a block-by-block basis, and code words in each ECC block,in each sector, or in each sector group, on a string-by-string basis;said system control means comprises: a collective-type means-basis ECCblock pipeline processing notification sub means for collectivelytransmitting ECC blocks which have been subjected to error correctiondownstream; for collectively storing ECC blocks to be processed next tosaid plural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block code word recognition sub meansfor selecting code words of the ECC blocks to be processed, inaccordance with the contents stored in said ECC-block-and-codeword-division storing means, in controlling a data transfer from saidbus control means to said syndrome calculating means, to said errordetecting means, and to said error correcting means for error detectionand error correction; in controlling the error correction done by saiderror correcting means; in controlling writing of error-corrected datato said ECC-block-basis buffer memory done by said bus control means; instoring mid-term results to said ECC-block-and-code word-divisionstoring means by said error detecting means; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein.
 27. The error correction device of claim11, wherein error correction is performed in parallel for data in aplurality of ECC blocks each having a structure where a plurality oferror correcting code words each comprising a data unit and a parityunit are arranged in vertical direction and horizontal direction so asto repeat error correction a plurality of number of times, and wherepredetermined data composed of a predetermined number of code words inthe vertical direction or the horizontal direction (data in thehorizontal direction are referred to as sector) as a unit are subjectedto the error correction; said buffer memory is an ECC-block-basis buffermemory for storing, on a block-by-block basis, ECC blocks to beprocessed in parallel; said storing means for storing mid-term resultsof an error detecting process generated by said error detecting means isan ECC-block-and-code word-division storing means for storing ECC blocksin process on a block-by-block basis, and code words in each ECC block,in each sector, or in each sector group, on a string-by-string basis;said system control means comprises: a collective-type means-basis ECCblock pipeline processing notification sub means for collectivelytransmitting ECC blocks which have been subjected to error correctiondownstream; for collectively storing ECC blocks to be processed next tosaid plural-ECC-block-division buffer memory; and for making the storageknown to said bus control means, said syndrome calculating means, saiderror detecting means, and said error correcting means; acollective-type means-basis ECC block code word recognition sub meansfor selecting code words of the ECC blocks to be processed, inaccordance with the contents stored in said ECC-block-and-codeword-division storing means, in controlling a data transfer from saidbus control means to said syndrome calculating means, to said errordetecting means, and to said error correcting means for error detectionand error correction; in controlling the error correction done by saiderror correcting means; in controlling writing of error-corrected datato said ECC-block-basis buffer memory done by said bus control means; instoring mid-term results to said ECC-block-and-code word-divisionstoring means by said error detecting means; and a collective-type ECCblock notification sub means in sub means-basis pipeline processing fornotifying said first error detecting sub means, said even-numbered errorcorrection sub means, said odd-numbered error correction sub means, saidnumber-of-times control sub means, and said DMA transfer instruction submeans contained in said system control means that the error-correctedECC blocks have been collectively transmitted downstream and new ECCblocks to be processed have been collectively stored in saidplural-ECC-block-division buffer memory, and further notifying thesesame sub means contained in said system control means of the ECC blockswhich are in process therein. 28-30. (canceled)
 31. The error correctiondevice of claim 7, further comprising: two buffer memories each having apredetermined capacity equivalent to one sector or one ECC block; abuffer memory storage means for alternately storing in said two buffermemories, in accordance with error correction speed, continuous data ofthe predetermined capacity which are a target of error correction andhave been read from a DVD or a CD-ROM; and an accessed buffer memoryswitch means for switching between said two buffer memories in order toread or write data as a target of error correction alternately in unitsof said predetermined capacity.
 32. The error correction device of claim9 further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 33. The error correction device of claim 10further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 34. The error correction device of claim 11further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 35. The error correction device of claim 12further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 36. The error correction device of claim 13further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 37. The error correction device of claim 14further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 38. The error correction device of claim 15further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 39. The error correction device of claim 16further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 40. The error correction device of claim 17further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 41. The error correction device of claim 18further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 42. The error correction device of claim 19further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 43. The error correction device of claim 20further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 44. The error correction device of claim 21further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 45. The error correction device of claim 22further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 46. The error correction device of claim 23further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 47. The error correction device of claim 24further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 48. The error correction device of claim 25further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 49. The error correction device of claim 26further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.
 50. The error correction device of claim 27further comprising: two buffer memories each having a predeterminedcapacity equivalent to one sector or one ECC block; a buffer memorystorage means for alternately storing in said two buffer memories, inaccordance with error correction speed, continuous data of thepredetermined capacity which are a target of error correction and havebeen read from a DVD or a CD-ROM; and an accessed buffer memory switchmeans for switching between said two buffer memories in order to read orwrite data as a target of error correction alternately in units of saidpredetermined capacity.